forked from OSchip/llvm-project
[X86] Add intrinsics for KADD instructions
These are intrinsics for supporting kadd builtins in clang. These builtins are already in gcc to implement intrinsics from icc. Though they are missing from the Intel Intrinsics Guide. This instruction adds two mask registers together as if they were scalar rather than a vXi1. We might be able to get away with a bitcast to scalar and a normal add instruction, but that would require DAG combine smarts in the backend to recoqnize add+bitcast. For now I'd prefer to go with the easiest implementation so we can get these builtins in to clang with good codegen. Differential Revision: https://reviews.llvm.org/D51370 llvm-svn: 340869
This commit is contained in:
Craig Topper
parent
9cca227d3e
commit
9401fd0ed2
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@ -2763,6 +2763,18 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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//===----------------------------------------------------------------------===//
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// AVX512
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// Mask ops
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let TargetPrefix = "x86" in {
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def int_x86_avx512_kadd_b : GCCBuiltin<"__builtin_ia32_kaddqi">,
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Intrinsic<[llvm_v8i1_ty], [llvm_v8i1_ty, llvm_v8i1_ty], [IntrNoMem]>;
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def int_x86_avx512_kadd_w : GCCBuiltin<"__builtin_ia32_kaddhi">,
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Intrinsic<[llvm_v16i1_ty], [llvm_v16i1_ty, llvm_v16i1_ty], [IntrNoMem]>;
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def int_x86_avx512_kadd_d : GCCBuiltin<"__builtin_ia32_kaddsi">,
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Intrinsic<[llvm_v32i1_ty], [llvm_v32i1_ty, llvm_v32i1_ty], [IntrNoMem]>;
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def int_x86_avx512_kadd_q : GCCBuiltin<"__builtin_ia32_kadddi">,
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Intrinsic<[llvm_v64i1_ty], [llvm_v64i1_ty, llvm_v64i1_ty], [IntrNoMem]>;
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}
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// Conversion ops
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_avx512_cvttss2si : GCCBuiltin<"__builtin_ia32_vcvttss2si32">,
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@ -404,6 +404,10 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86_INTRINSIC_DATA(avx512_fpclass_ps_128, FPCLASS, X86ISD::VFPCLASS, 0),
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X86_INTRINSIC_DATA(avx512_fpclass_ps_256, FPCLASS, X86ISD::VFPCLASS, 0),
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X86_INTRINSIC_DATA(avx512_fpclass_ps_512, FPCLASS, X86ISD::VFPCLASS, 0),
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X86_INTRINSIC_DATA(avx512_kadd_b, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_kadd_d, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_kadd_q, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_kadd_w, INTR_TYPE_2OP, X86ISD::KADD, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_sd_round, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::FADDS_RND, 0),
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X86_INTRINSIC_DATA(avx512_mask_add_ss_round, INTR_TYPE_SCALAR_MASK_RM,
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@ -2,6 +2,62 @@
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64
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define i32 @test_int_x86_avx512_kadd_d(<32 x i16> %A, <32 x i16> %B) nounwind {
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; CHECK-LABEL: test_int_x86_avx512_kadd_d:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vptestmw %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x26,0xc0]
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; CHECK-NEXT: vptestmw %zmm1, %zmm1, %k1 # encoding: [0x62,0xf2,0xf5,0x48,0x26,0xc9]
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; CHECK-NEXT: kaddd %k1, %k0, %k0 # encoding: [0xc4,0xe1,0xfd,0x4a,0xc1]
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; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
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; CHECK-NEXT: kortestd %k0, %k0 # encoding: [0xc4,0xe1,0xf9,0x98,0xc0]
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; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
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; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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entry:
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%0 = icmp ne <32 x i16> %A, zeroinitializer
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%1 = icmp ne <32 x i16> %B, zeroinitializer
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%2 = call <32 x i1> @llvm.x86.avx512.kadd.d(<32 x i1> %0, <32 x i1> %1)
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%3 = bitcast <32 x i1> %2 to i32
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%4 = icmp eq i32 %3, 0
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%5 = zext i1 %4 to i32
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ret i32 %5
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}
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declare <32 x i1> @llvm.x86.avx512.kadd.d(<32 x i1>, <32 x i1>)
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define i32 @test_int_x86_avx512_kadd_q(<64 x i8> %A, <64 x i8> %B) nounwind {
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; X86-LABEL: test_int_x86_avx512_kadd_q:
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; X86: # %bb.0: # %entry
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; X86-NEXT: vptestmb %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0x7d,0x48,0x26,0xc0]
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; X86-NEXT: vptestmb %zmm1, %zmm1, %k1 # encoding: [0x62,0xf2,0x75,0x48,0x26,0xc9]
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; X86-NEXT: kaddq %k1, %k0, %k0 # encoding: [0xc4,0xe1,0xfc,0x4a,0xc1]
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; X86-NEXT: kshiftrq $32, %k0, %k1 # encoding: [0xc4,0xe3,0xf9,0x31,0xc8,0x20]
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; X86-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
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; X86-NEXT: kortestd %k1, %k0 # encoding: [0xc4,0xe1,0xf9,0x98,0xc1]
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; X86-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
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; X86-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; X86-NEXT: retl # encoding: [0xc3]
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;
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; X64-LABEL: test_int_x86_avx512_kadd_q:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vptestmb %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0x7d,0x48,0x26,0xc0]
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; X64-NEXT: vptestmb %zmm1, %zmm1, %k1 # encoding: [0x62,0xf2,0x75,0x48,0x26,0xc9]
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; X64-NEXT: kaddq %k1, %k0, %k0 # encoding: [0xc4,0xe1,0xfc,0x4a,0xc1]
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; X64-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
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; X64-NEXT: kortestq %k0, %k0 # encoding: [0xc4,0xe1,0xf8,0x98,0xc0]
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; X64-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
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; X64-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; X64-NEXT: retq # encoding: [0xc3]
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entry:
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%0 = icmp ne <64 x i8> %A, zeroinitializer
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%1 = icmp ne <64 x i8> %B, zeroinitializer
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%2 = call <64 x i1> @llvm.x86.avx512.kadd.q(<64 x i1> %0, <64 x i1> %1)
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%3 = bitcast <64 x i1> %2 to i64
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%4 = icmp eq i64 %3, 0
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%5 = zext i1 %4 to i32
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ret i32 %5
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}
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declare <64 x i1> @llvm.x86.avx512.kadd.q(<64 x i1>, <64 x i1>)
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define <32 x i16> @test_mask_packs_epi32_rr_512(<16 x i32> %a, <16 x i32> %b) {
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; CHECK-LABEL: test_mask_packs_epi32_rr_512:
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; CHECK: # %bb.0:
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@ -4,6 +4,50 @@
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX512DQ,X64-AVX512DQ
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX512DQVL,X64-AVX512DQVL
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define i32 @test_int_x86_avx512_kadd_w(<16 x i32> %A, <16 x i32> %B) nounwind {
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; CHECK-LABEL: test_int_x86_avx512_kadd_w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0x7d,0x48,0x27,0xc0]
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; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1 # encoding: [0x62,0xf2,0x75,0x48,0x27,0xc9]
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; CHECK-NEXT: kaddw %k1, %k0, %k0 # encoding: [0xc5,0xfc,0x4a,0xc1]
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; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
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; CHECK-NEXT: kortestw %k0, %k0 # encoding: [0xc5,0xf8,0x98,0xc0]
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; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
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; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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entry:
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%0 = icmp ne <16 x i32> %A, zeroinitializer
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%1 = icmp ne <16 x i32> %B, zeroinitializer
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%2 = call <16 x i1> @llvm.x86.avx512.kadd.w(<16 x i1> %0, <16 x i1> %1)
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%3 = bitcast <16 x i1> %2 to i16
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%4 = icmp eq i16 %3, 0
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%5 = zext i1 %4 to i32
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ret i32 %5
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}
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declare <16 x i1> @llvm.x86.avx512.kadd.w(<16 x i1>, <16 x i1>)
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define i32 @test_int_x86_avx512_kadd_b(<8 x i64> %A, <8 x i64> %B) nounwind {
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; CHECK-LABEL: test_int_x86_avx512_kadd_b:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0]
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; CHECK-NEXT: vptestmq %zmm1, %zmm1, %k1 # encoding: [0x62,0xf2,0xf5,0x48,0x27,0xc9]
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; CHECK-NEXT: kaddb %k1, %k0, %k0 # encoding: [0xc5,0xfd,0x4a,0xc1]
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; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
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; CHECK-NEXT: kortestb %k0, %k0 # encoding: [0xc5,0xf9,0x98,0xc0]
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; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
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; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
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entry:
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%0 = icmp ne <8 x i64> %A, zeroinitializer
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%1 = icmp ne <8 x i64> %B, zeroinitializer
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%2 = call <8 x i1> @llvm.x86.avx512.kadd.b(<8 x i1> %0, <8 x i1> %1)
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%3 = bitcast <8 x i1> %2 to i8
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%4 = icmp eq i8 %3, 0
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%5 = zext i1 %4 to i32
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ret i32 %5
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}
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declare <8 x i1> @llvm.x86.avx512.kadd.b(<8 x i1>, <8 x i1>)
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declare <8 x i64> @llvm.x86.avx512.mask.cvtpd2qq.512(<8 x double>, <8 x i64>, i8, i32)
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define <8 x i64>@test_int_x86_avx512_mask_cvt_pd2qq_512(<8 x double> %x0, <8 x i64> %x1, i8 %x2) {
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