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t2BR_JT is mov pc, it's 2 byte long, not 4. 

llvm-svn: 77744
This commit is contained in:
Evan Cheng 2009-07-31 22:22:22 +00:00
parent 9eb3f88048
commit 95d6325859
1 changed files with 9 additions and 9 deletions
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18
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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@ -410,6 +410,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
const TargetInstrDesc &TID = MI->getDesc(); const TargetInstrDesc &TID = MI->getDesc();
unsigned TSFlags = TID.TSFlags; unsigned TSFlags = TID.TSFlags;
unsigned Opc = MI->getOpcode();
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default: { default: {
// If this machine instr is an inline asm, measure it. // If this machine instr is an inline asm, measure it.
@ -417,7 +418,7 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName()); return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
if (MI->isLabel()) if (MI->isLabel())
return 0; return 0;
switch (MI->getOpcode()) { switch (Opc) {
default: default:
llvm_unreachable("Unknown or unset size field for instr!"); llvm_unreachable("Unknown or unset size field for instr!");
case TargetInstrInfo::IMPLICIT_DEF: case TargetInstrInfo::IMPLICIT_DEF:
@ -432,28 +433,25 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction. case ARMII::Size4Bytes: return 4; // ARM / Thumb2 instruction.
case ARMII::Size2Bytes: return 2; // Thumb1 instruction. case ARMII::Size2Bytes: return 2; // Thumb1 instruction.
case ARMII::SizeSpecial: { case ARMII::SizeSpecial: {
bool IsThumb1JT = false; switch (Opc) {
switch (MI->getOpcode()) {
case ARM::CONSTPOOL_ENTRY: case ARM::CONSTPOOL_ENTRY:
// If this machine instr is a constant pool entry, its size is recorded as // If this machine instr is a constant pool entry, its size is recorded as
// operand #2. // operand #2.
return MI->getOperand(2).getImm(); return MI->getOperand(2).getImm();
case ARM::Int_eh_sjlj_setjmp: case ARM::Int_eh_sjlj_setjmp:
return 12; return 12;
case ARM::tBR_JTr:
IsThumb1JT = true;
// Fallthrough
case ARM::BR_JTr: case ARM::BR_JTr:
case ARM::BR_JTm: case ARM::BR_JTm:
case ARM::BR_JTadd: case ARM::BR_JTadd:
case ARM::tBR_JTr:
case ARM::t2BR_JT: case ARM::t2BR_JT:
case ARM::t2TBB: case ARM::t2TBB:
case ARM::t2TBH: { case ARM::t2TBH: {
// These are jumptable branches, i.e. a branch followed by an inlined // These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries. For TBB, each // jumptable. The size is 4 + 4 * number of entries. For TBB, each
// entry is one byte; TBH two byte each. // entry is one byte; TBH two byte each.
unsigned EntrySize = (MI->getOpcode() == ARM::t2TBB) unsigned EntrySize = (Opc == ARM::t2TBB)
? 1 : ((MI->getOpcode() == ARM::t2TBH) ? 2 : 4); ? 1 : ((Opc == ARM::t2TBH) ? 2 : 4);
unsigned NumOps = TID.getNumOperands(); unsigned NumOps = TID.getNumOperands();
MachineOperand JTOP = MachineOperand JTOP =
MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
@ -468,7 +466,9 @@ unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
// FIXME: If we know the size of the function is less than (1 << 16) *2 // FIXME: If we know the size of the function is less than (1 << 16) *2
// bytes, we can use 16-bit entries instead. Then there won't be an // bytes, we can use 16-bit entries instead. Then there won't be an
// alignment issue. // alignment issue.
return getNumJTEntries(JT, JTI) * EntrySize + (IsThumb1JT ? 2 : 4); unsigned InstSize = (Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT)
? 2 : 4;
return getNumJTEntries(JT, JTI) * EntrySize + InstSize;
} }
default: default:
// Otherwise, pseudo-instruction sizes are zero. // Otherwise, pseudo-instruction sizes are zero.