Add instruction encodings / disassembly support for u6 / lu6 instructions.

llvm-svn: 173086

llvm/lib/Target/XCore/XCoreInstrFormats.td

@@ -107,12 +107,22 @@ class _FLRU6<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{9-0} = b{15-6};
 }
 
-class _FU6<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _FU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<2, outs, ins, asmstr, pattern> {
+  bits<6> a;
+
+  let Inst{15-6} = opc;
+  let Inst{5-0} = a;
 }
 
-class _FLU6<dag outs, dag ins, string asmstr, list<dag> pattern>
+class _FLU6<bits<10> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
     : InstXCore<4, outs, ins, asmstr, pattern> {
+  bits<16> a;
+
+  let Inst{31-22} = opc;
+  let Inst{21-16} = a{5-0};
+  let Inst{15-10} = 0b111100;
+  let Inst{9-0} = a{15-6};
 }
 
 class _FU10<dag outs, dag ins, string asmstr, list<dag> pattern>

llvm/lib/Target/XCore/XCoreInstrInfo.td

@@ -288,36 +288,23 @@ multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
 }
 
 // U6
-multiclass FU6_LU6<string OpcStr, SDNode OpNode> {
+multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
-  def _u6: _FU6<
+  def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
-                 (outs), (ins i32imm:$b),
+                [(OpNode immU6:$a)]>;
-                 !strconcat(OpcStr, " $b"),
+  def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
-                 [(OpNode immU6:$b)]>;
+                  [(OpNode immU16:$a)]>;
-  def _lu6: _FLU6<
-                 (outs), (ins i32imm:$b),
-                 !strconcat(OpcStr, " $b"),
-                 [(OpNode immU16:$b)]>;
-}
-multiclass FU6_LU6_int<string OpcStr, Intrinsic Int> {
-  def _u6: _FU6<
-                 (outs), (ins i32imm:$b),
-                 !strconcat(OpcStr, " $b"),
-                 [(Int immU6:$b)]>;
-  def _lu6: _FLU6<
-                 (outs), (ins i32imm:$b),
-                 !strconcat(OpcStr, " $b"),
-                 [(Int immU16:$b)]>;
 }
 
-multiclass FU6_LU6_np<string OpcStr> {
+multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
-  def _u6: _FU6<
+  def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
-                 (outs), (ins i32imm:$b),
+                [(Int immU6:$a)]>;
-                 !strconcat(OpcStr, " $b"),
+  def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
-                 []>;
+                  [(Int immU16:$a)]>;
-  def _lu6: _FLU6<
+}
-                 (outs), (ins i32imm:$b),
+
-                 !strconcat(OpcStr, " $b"),
+multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
-                 []>;
+  def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
+  def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
 }
 
 // U10
@@ -628,60 +615,46 @@ defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
 // U6
 let Defs = [SP], Uses = [SP] in {
 let neverHasSideEffects = 1 in
-defm EXTSP : FU6_LU6_np<"extsp">;
+defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
 let mayStore = 1 in
-defm ENTSP : FU6_LU6_np<"entsp">;
+defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
 
 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
-defm RETSP : FU6_LU6<"retsp", XCoreRetsp>;
+defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
 }
 }
 
 // TODO extdp, kentsp, krestsp, blat
 // getsr, kalli
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
-def BRBU_u6 : _FU6<
+def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
-                 (outs),
-                 (ins brtarget:$target),
-                 "bu $target",
-                 []>;
 
-def BRBU_lu6 : _FLU6<
+def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
-                 (outs),
-                 (ins brtarget:$target),
-                 "bu $target",
-                 []>;
 
-def BRFU_u6 : _FU6<
+def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
-                 (outs),
-                 (ins brtarget:$target),
-                 "bu $target",
-                 []>;
 
-def BRFU_lu6 : _FLU6<
+def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
-                 (outs),
-                 (ins brtarget:$target),
-                 "bu $target",
-                 []>;
 }
 
 //let Uses = [CP] in ...
 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
-def LDAWCP_u6: _FU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]", []>;
+def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
+                    []>;
 
 let Defs = [R11], isReMaterializable = 1 in
-def LDAWCP_lu6: _FLU6<(outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
+def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
                       [(set R11, ADDRcpii:$a)]>;
 
-defm SETSR : FU6_LU6_int<"setsr", int_xcore_setsr>;
+defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
 
-defm CLRSR : FU6_LU6_int<"clrsr", int_xcore_clrsr>;
+defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
 
 // setsr may cause a branch if it is used to enable events. clrsr may
 // branch if it is executed while events are enabled.
-let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in {
+let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
-defm SETSR_branch : FU6_LU6_np<"setsr">;
+    isCodeGenOnly = 1 in {
-defm CLRSR_branch : FU6_LU6_np<"clrsr">;
+defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
+defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
 }
 
 // U10

llvm/test/MC/Disassembler/XCore/xcore.txt

@@ -392,3 +392,53 @@
 
 # CHECK: stw r0, sp[8761]
 0x88 0xf0 0x39 0x54
+
+# u6 / lu6 instructions
+
+# CHECK: bu -20
+0x14 0x77
+
+# CHECK: bu -1000
+0x0f 0xf0 0x28 0x77
+
+# CHECK: bu 24
+0x18 0x73
+
+# CHECK: bu 2231
+0x22 0xf0 0x37 0x73
+
+# CHECK: extsp 9
+0x89 0x77
+
+# CHECK: extsp 5721
+0x59 0xf0 0x99 0x77
+
+# CHECK: clrsr 60
+0x3c 0x7b
+
+# CHECK: clrsr 64391
+0xee 0xf3 0x07 0x7b
+
+# CHECK: entsp 1
+0x41 0x77
+
+# CHECK: entsp 70
+0x01 0xf0 0x46 0x77
+
+# CHECK: ldaw r11, cp[5]
+0x45 0x7f
+
+# CHECK: ldaw r11, cp[33000]
+0x03 0xf2 0x68 0x7f
+
+# CHECK: retsp 40
+0xe8 0x77
+
+# CHECK: retsp 52010
+0x2c 0xf3 0xea 0x77
+
+# CHECK: setsr 42
+0x6a 0x7b
+
+# CHECK: setsr 21863
+0x55 0xf1 0x67 0x7b