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[DAGCombiner] Enable AND combines of splatted constant vectors 

Allow AND combines to use a vector splatted constant as well as a constant scalar.

Preliminary part of D24253.

llvm-svn: 280926
This commit is contained in:
Simon Pilgrim 2016-09-08 12:36:39 +00:00
parent 16853bb00f
commit a01ee07a19
2 changed files with 9 additions and 11 deletions
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10
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3099,7 +3099,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// fold (and c1, c2) -> c1&c2 // fold (and c1, c2) -> c1&c2
ConstantSDNode *N0C = getAsNonOpaqueConstant(N0); ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); ConstantSDNode *N1C = isConstOrConstSplat(N1);
if (N0C && N1C && !N1C->isOpaque()) if (N0C && N1C && !N1C->isOpaque())
return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C); return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
// canonicalize constant to RHS // canonicalize constant to RHS
@ -3119,14 +3119,14 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
return RAND; return RAND;
// fold (and (or x, C), D) -> D if (C & D) == D // fold (and (or x, C), D) -> D if (C & D) == D
if (N1C && N0.getOpcode() == ISD::OR) if (N1C && N0.getOpcode() == ISD::OR)
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) if (ConstantSDNode *ORI = isConstOrConstSplat(N0.getOperand(1)))
if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
return N1; return N1;
// fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
SDValue N0Op0 = N0.getOperand(0); SDValue N0Op0 = N0.getOperand(0);
APInt Mask = ~N1C->getAPIntValue(); APInt Mask = ~N1C->getAPIntValue();
Mask = Mask.trunc(N0Op0.getValueSizeInBits()); Mask = Mask.trunc(N0Op0.getScalarValueSizeInBits());
if (DAG.MaskedValueIsZero(N0Op0, Mask)) { if (DAG.MaskedValueIsZero(N0Op0, Mask)) {
SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
N0.getValueType(), N0Op0); N0.getValueType(), N0Op0);
@ -3177,7 +3177,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// that will apply equally to all members of the vector, so AND all the // that will apply equally to all members of the vector, so AND all the
// lanes of the constant together. // lanes of the constant together.
EVT VT = Vector->getValueType(0); EVT VT = Vector->getValueType(0);
unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); unsigned BitWidth = VT.getScalarType().getSizeInBits();
// If the splat value has been compressed to a bitlength lower // If the splat value has been compressed to a bitlength lower
// than the size of the vector lane, we need to re-expand it to // than the size of the vector lane, we need to re-expand it to
@ -3251,7 +3251,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
// fold (and (load x), 255) -> (zextload x, i8) // fold (and (load x), 255) -> (zextload x, i8)
// fold (and (extload x, i16), 255) -> (zextload x, i8) // fold (and (extload x, i16), 255) -> (zextload x, i8)
// fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8)
if (N1C && (N0.getOpcode() == ISD::LOAD || if (!VT.isVector() && N1C && (N0.getOpcode() == ISD::LOAD ||
(N0.getOpcode() == ISD::ANY_EXTEND && (N0.getOpcode() == ISD::ANY_EXTEND &&
N0.getOperand(0).getOpcode() == ISD::LOAD))) { N0.getOperand(0).getOpcode() == ISD::LOAD))) {
bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND;

6
llvm/test/CodeGen/X86/combine-and.ll
View File

@ -186,8 +186,7 @@ define <4 x i32> @test17(<4 x i32> %A, <4 x i32> %B) {
define <2 x i64> @and_or_v2i64(<2 x i64> %a0) { define <2 x i64> @and_or_v2i64(<2 x i64> %a0) {
; CHECK-LABEL: and_or_v2i64: ; CHECK-LABEL: and_or_v2i64:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: orps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [8,8]
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = or <2 x i64> %a0, <i64 255, i64 255> %1 = or <2 x i64> %a0, <i64 255, i64 255>
%2 = and <2 x i64> %1, <i64 8, i64 8> %2 = and <2 x i64> %1, <i64 8, i64 8>
@ -197,8 +196,7 @@ define <2 x i64> @and_or_v2i64(<2 x i64> %a0) {
define <4 x i32> @and_or_v4i32(<4 x i32> %a0) { define <4 x i32> @and_or_v4i32(<4 x i32> %a0) {
; CHECK-LABEL: and_or_v4i32: ; CHECK-LABEL: and_or_v4i32:
; CHECK: # BB#0: ; CHECK: # BB#0:
; CHECK-NEXT: orps {{.*}}(%rip), %xmm0 ; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3]
; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%1 = or <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15> %1 = or <4 x i32> %a0, <i32 15, i32 15, i32 15, i32 15>
%2 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3> %2 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>