wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[AArch64] Check for simple type in FPToUInt 

DAGCombiner was hitting a SimpleType assertion when trying to combine
a v3f32 before type legalization.

bugzilla: https://bugs.llvm.org/show_bug.cgi?id=41916

Differential Revision: https://reviews.llvm.org/D62734

llvm-svn: 362365
This commit is contained in:
Sam Parker 2019-06-03 08:49:17 +00:00
parent bcd542881d
commit a0bd6f8a1a
2 changed files with 20 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -9206,6 +9206,9 @@ static SDValue performFpToIntCombine(SDNode *N, SelectionDAG &DAG,
if (!Subtarget->hasNEON())
return SDValue();
if (!N->getValueType(0).isSimple())
return SDValue();
SDValue Op = N->getOperand(0);
if (!Op.getValueType().isVector() || !Op.getValueType().isSimple() ||
Op.getOpcode() != ISD::FMUL)

17
llvm/test/CodeGen/AArch64/v3f-to-int.ll Normal file
View File

@ -0,0 +1,17 @@
; RUN: llc -mtriple=aarch64--linux-eabi %s -o - | FileCheck %s
; CHECK-LABEL: convert_v3f32
; CHECK: strb
; CHECK: strh
define void @convert_v3f32() {
entry:
br label %bb
bb:
%0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
%1 = fmul reassoc nnan ninf nsz contract afn <3 x float> %0, <float 2.550000e+02, float 2.550000e+02, float 2.550000e+02>
%2 = fptoui <3 x float> %1 to <3 x i8>
%3 = bitcast i8* undef to <3 x i8>*
store <3 x i8> %2, <3 x i8>* %3, align 1
ret void
}