[mips] Add support to '.set mips64r2'.

The '.set mips64r2' directive enables the feature Mips:FeatureMips64r2
from assembly. Note that it doesn't modify the ELF header as opposed
to the use of -mips64r2 from the command-line. The reason for this
is that we want to be as compatible as possible with existing assemblers
like GAS.

llvm-svn: 204815

llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

@@ -2489,6 +2489,10 @@ bool MipsAsmParser::parseSetFeature(uint64_t Feature) {
       setFeatureBits(Mips::FeatureMips32r2, "mips32r2");
       getTargetStreamer().emitDirectiveSetMips32R2();
     break;
+    case Mips::FeatureMips64r2:
+      setFeatureBits(Mips::FeatureMips64r2, "mips64r2");
+      getTargetStreamer().emitDirectiveSetMips64R2();
+    break;
   }
   return false;
 }
@@ -2522,6 +2526,8 @@ bool MipsAsmParser::parseDirectiveSet() {
       return parseSetFeature(Mips::FeatureMicroMips);
   } else if (Tok.getString() == "mips32r2") {
       return parseSetFeature(Mips::FeatureMips32r2);
+  } else if (Tok.getString() == "mips64r2") {
+      return parseSetFeature(Mips::FeatureMips64r2);
   } else if (Tok.getString() == "dsp") {
       return parseSetFeature(Mips::FeatureDSP);
   } else {

llvm/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp

@@ -105,6 +105,10 @@ void MipsTargetAsmStreamer::emitDirectiveSetMips32R2() {
   OS << "\t.set\tmips32r2\n";
 }
 
+void MipsTargetAsmStreamer::emitDirectiveSetMips64R2() {
+  OS << "\t.set\tmips64r2\n";
+}
+
 void MipsTargetAsmStreamer::emitDirectiveSetDsp() {
   OS << "\t.set\tdsp\n";
 }
@@ -355,6 +359,10 @@ void MipsTargetELFStreamer::emitDirectiveSetMips32R2() {
   // No action required for ELF output.
 }
 
+void MipsTargetELFStreamer::emitDirectiveSetMips64R2() {
+  // No action required for ELF output.
+}
+
 void MipsTargetELFStreamer::emitDirectiveSetDsp() {
   // No action required for ELF output.
 }

llvm/lib/Target/Mips/MipsTargetStreamer.h

@@ -42,6 +42,7 @@ public:
   virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) = 0;
 
   virtual void emitDirectiveSetMips32R2() = 0;
+  virtual void emitDirectiveSetMips64R2() = 0;
   virtual void emitDirectiveSetDsp() = 0;
 };
 
@@ -74,6 +75,7 @@ public:
   virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
 
   virtual void emitDirectiveSetMips32R2();
+  virtual void emitDirectiveSetMips64R2();
   virtual void emitDirectiveSetDsp();
 };
 
@@ -115,6 +117,7 @@ public:
   virtual void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff);
 
   virtual void emitDirectiveSetMips32R2();
+  virtual void emitDirectiveSetMips64R2();
   virtual void emitDirectiveSetDsp();
 };
 }

llvm/test/MC/Mips/mips_directives.s

@@ -65,6 +65,11 @@ $BB0_4:
     luxc1   $f0, $6($5)
     lwxc1   $f6, $2($5)
 
+# CHECK: .set mips64r2
+# CHECK: drotr $9, $6, 30              # encoding: [0x00,0x26,0x4f,0xba]
+    .set mips64r2
+    drotr   $9, $6, 30
+
 # CHECK:   .set dsp
 # CHECK:   lbux    $7, $10($11)         # encoding: [0x7d,0x6a,0x39,0x8a]
 # CHECK:   lhx     $5, $6($7)           # encoding: [0x7c,0xe6,0x29,0x0a]