wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[X86] Disable a DAG combine to allow packed AVX512DQ instructions to be consistently used for i64->float/double conversions. 

Summary: We already get this right if the i64 didn't come from a load.

Reviewers: RKSimon

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47439

llvm-svn: 333393
This commit is contained in:
Craig Topper 2018-05-29 06:22:45 +00:00
parent 07c9ec6f2e
commit a34f8731c7
2 changed files with 77 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -37729,6 +37729,11 @@ static SDValue combineSIntToFP(SDNode *N, SelectionDAG &DAG,
if (VT == MVT::f16 || VT == MVT::f128)
return SDValue();
// If we have AVX512DQ we can use packed conversion instructions unless
// the VT is f80.
if (Subtarget.hasDQI() && VT != MVT::f80)
return SDValue();
if (!Ld->isVolatile() && !VT.isVector() &&
ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
!Subtarget.is64Bit() && LdVT == MVT::i64) {

92
llvm/test/CodeGen/X86/scalar-int-to-fp.ll
View File

@ -410,20 +410,42 @@ define float @u64_to_f(i64 %a) nounwind {
}
define float @s64_to_f(i64 %a) nounwind {
; AVX512_32-LABEL: s64_to_f:
; AVX512_32: # %bb.0:
; AVX512_32-NEXT: pushl %eax
; AVX512_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512_32-NEXT: fstps (%esp)
; AVX512_32-NEXT: flds (%esp)
; AVX512_32-NEXT: popl %eax
; AVX512_32-NEXT: retl
; AVX512DQVL_32-LABEL: s64_to_f:
; AVX512DQVL_32: # %bb.0:
; AVX512DQVL_32-NEXT: pushl %eax
; AVX512DQVL_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQVL_32-NEXT: vcvtqq2ps %ymm0, %xmm0
; AVX512DQVL_32-NEXT: vmovss %xmm0, (%esp)
; AVX512DQVL_32-NEXT: flds (%esp)
; AVX512DQVL_32-NEXT: popl %eax
; AVX512DQVL_32-NEXT: vzeroupper
; AVX512DQVL_32-NEXT: retl
;
; AVX512_64-LABEL: s64_to_f:
; AVX512_64: # %bb.0:
; AVX512_64-NEXT: vcvtsi2ssq %rdi, %xmm0, %xmm0
; AVX512_64-NEXT: retq
;
; AVX512DQ_32-LABEL: s64_to_f:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %eax
; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtqq2ps %zmm0, %ymm0
; AVX512DQ_32-NEXT: vmovss %xmm0, (%esp)
; AVX512DQ_32-NEXT: flds (%esp)
; AVX512DQ_32-NEXT: popl %eax
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
;
; AVX512F_32-LABEL: s64_to_f:
; AVX512F_32: # %bb.0:
; AVX512F_32-NEXT: pushl %eax
; AVX512F_32-NEXT: fildll {{[0-9]+}}(%esp)
; AVX512F_32-NEXT: fstps (%esp)
; AVX512F_32-NEXT: flds (%esp)
; AVX512F_32-NEXT: popl %eax
; AVX512F_32-NEXT: retl
;
; SSE2_32-LABEL: s64_to_f:
; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %eax
@ -656,24 +678,54 @@ define double @u64_to_d(i64 %a) nounwind {
}
define double @s64_to_d(i64 %a) nounwind {
; AVX512_32-LABEL: s64_to_d:
; AVX512_32: # %bb.0:
; AVX512_32-NEXT: pushl %ebp
; AVX512_32-NEXT: movl %esp, %ebp
; AVX512_32-NEXT: andl $-8, %esp
; AVX512_32-NEXT: subl $8, %esp
; AVX512_32-NEXT: fildll 8(%ebp)
; AVX512_32-NEXT: fstpl (%esp)
; AVX512_32-NEXT: fldl (%esp)
; AVX512_32-NEXT: movl %ebp, %esp
; AVX512_32-NEXT: popl %ebp
; AVX512_32-NEXT: retl
; AVX512DQVL_32-LABEL: s64_to_d:
; AVX512DQVL_32: # %bb.0:
; AVX512DQVL_32-NEXT: pushl %ebp
; AVX512DQVL_32-NEXT: movl %esp, %ebp
; AVX512DQVL_32-NEXT: andl $-8, %esp
; AVX512DQVL_32-NEXT: subl $8, %esp
; AVX512DQVL_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQVL_32-NEXT: vcvtqq2pd %ymm0, %ymm0
; AVX512DQVL_32-NEXT: vmovlps %xmm0, (%esp)
; AVX512DQVL_32-NEXT: fldl (%esp)
; AVX512DQVL_32-NEXT: movl %ebp, %esp
; AVX512DQVL_32-NEXT: popl %ebp
; AVX512DQVL_32-NEXT: vzeroupper
; AVX512DQVL_32-NEXT: retl
;
; AVX512_64-LABEL: s64_to_d:
; AVX512_64: # %bb.0:
; AVX512_64-NEXT: vcvtsi2sdq %rdi, %xmm0, %xmm0
; AVX512_64-NEXT: retq
;
; AVX512DQ_32-LABEL: s64_to_d:
; AVX512DQ_32: # %bb.0:
; AVX512DQ_32-NEXT: pushl %ebp
; AVX512DQ_32-NEXT: movl %esp, %ebp
; AVX512DQ_32-NEXT: andl $-8, %esp
; AVX512DQ_32-NEXT: subl $8, %esp
; AVX512DQ_32-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
; AVX512DQ_32-NEXT: vcvtqq2pd %zmm0, %zmm0
; AVX512DQ_32-NEXT: vmovlps %xmm0, (%esp)
; AVX512DQ_32-NEXT: fldl (%esp)
; AVX512DQ_32-NEXT: movl %ebp, %esp
; AVX512DQ_32-NEXT: popl %ebp
; AVX512DQ_32-NEXT: vzeroupper
; AVX512DQ_32-NEXT: retl
;
; AVX512F_32-LABEL: s64_to_d:
; AVX512F_32: # %bb.0:
; AVX512F_32-NEXT: pushl %ebp
; AVX512F_32-NEXT: movl %esp, %ebp
; AVX512F_32-NEXT: andl $-8, %esp
; AVX512F_32-NEXT: subl $8, %esp
; AVX512F_32-NEXT: fildll 8(%ebp)
; AVX512F_32-NEXT: fstpl (%esp)
; AVX512F_32-NEXT: fldl (%esp)
; AVX512F_32-NEXT: movl %ebp, %esp
; AVX512F_32-NEXT: popl %ebp
; AVX512F_32-NEXT: retl
;
; SSE2_32-LABEL: s64_to_d:
; SSE2_32: # %bb.0:
; SSE2_32-NEXT: pushl %ebp