forked from OSchip/llvm-project
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497311ab99
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a39da09eb6
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@ -170,7 +170,11 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Special register classes for predicates and the M0 register
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// Special register classes for predicates and the M0 register
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def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)>;
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def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
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let CopyCost = -1; // Theoretically it is possible to read from SCC,
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// but it should never be necessary.
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}
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def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
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def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
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def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
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def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
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def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
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