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Revert r274347 "[ARM] Refactor Thumb2 mul instruction descs" 

This caused PR28387: Assertion "#operands for dag node doesn't match .td file!"

llvm-svn: 274367
This commit is contained in:
Hans Wennborg 2016-07-01 17:26:42 +00:00
parent 63a27afae3
commit a3bb5f1594
1 changed files with 322 additions and 139 deletions
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453
llvm/lib/Target/ARM/ARMInstrThumb2.td
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@ -536,9 +536,9 @@ class T2FourReg<dag oops, dag iops, InstrItinClass itin,
} }
class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
string opc, list<dag> pattern> dag oops, dag iops, InstrItinClass itin,
: T2I<(outs rGPR:$RdLo, rGPR:$RdHi), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, string opc, string asm, list<dag> pattern>
opc, "\t$RdLo, $RdHi, $Rn, $Rm", pattern> { : T2I<oops, iops, itin, opc, asm, pattern> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
@ -552,11 +552,10 @@ class T2MulLong<bits<3> opc22_20, bits<4> opc7_4,
let Inst{7-4} = opc7_4; let Inst{7-4} = opc7_4;
let Inst{3-0} = Rm; let Inst{3-0} = Rm;
} }
class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4, string opc> class T2MlaLong<bits<3> opc22_20, bits<4> opc7_4,
: T2I<(outs rGPR:$RdLo, rGPR:$RdHi), dag oops, dag iops, InstrItinClass itin,
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64, string opc, string asm, list<dag> pattern>
opc, "\t$RdLo, $RdHi, $Rn, $Rm", []>, : T2I<oops, iops, itin, opc, asm, pattern> {
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi"> {
bits<4> RdLo; bits<4> RdLo;
bits<4> RdHi; bits<4> RdHi;
bits<4> Rn; bits<4> Rn;
@ -2545,183 +2544,367 @@ def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
let Inst{7-4} = 0b0000; // Multiply let Inst{7-4} = 0b0000; // Multiply
} }
class T2FourRegMLA<bits<4> op7_4, string opc, list<dag> pattern> def t2MLA: T2FourReg<
: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, "mla", "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]>,
Requires<[IsThumb2, UseMulOps]> { Requires<[IsThumb2, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000; let Inst{22-20} = 0b000;
let Inst{7-4} = op7_4; let Inst{7-4} = 0b0000; // Multiply
} }
def t2MLA : T2FourRegMLA<0b0000, "mla", def t2MLS: T2FourReg<
[(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
rGPR:$Ra))]>; "mls", "\t$Rd, $Rn, $Rm, $Ra",
def t2MLS: T2FourRegMLA<0b0001, "mls", [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]>,
[(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, Requires<[IsThumb2, UseMulOps]> {
rGPR:$Rm)))]>; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b000;
let Inst{7-4} = 0b0001; // Multiply and Subtract
}
// Extra precision multiplies with low / high results // Extra precision multiplies with low / high results
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
let isCommutable = 1 in { let isCommutable = 1 in {
def t2SMULL : T2MulLong<0b000, 0b0000, "smull", []>; def t2SMULL : T2MulLong<0b000, 0b0000,
def t2UMULL : T2MulLong<0b010, 0b0000, "umull", []>; (outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
def t2UMULL : T2MulLong<0b010, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64,
"umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
} // isCommutable } // isCommutable
// Multiply + accumulate // Multiply + accumulate
def t2SMLAL : T2MlaLong<0b100, 0b0000, "smlal">; def t2SMLAL : T2MlaLong<0b100, 0b0000,
def t2UMLAL : T2MlaLong<0b110, 0b0000, "umlal">; (outs rGPR:$RdLo, rGPR:$RdHi),
def t2UMAAL : T2MulLong<0b110, 0b0110, "umaal", []>, (ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMLAL : T2MlaLong<0b110, 0b0000,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">;
def t2UMAAL : T2MulLong<0b110, 0b0110,
(outs rGPR:$RdLo, rGPR:$RdHi),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$RLo, rGPR:$RHi), IIC_iMAC64,
"umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
RegConstraint<"$RLo = $RdLo, $RHi = $RdHi">,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
} // hasSideEffects } // hasSideEffects
// Rounding variants of the below included for disassembly only // Rounding variants of the below included for disassembly only
// Most significant word multiply // Most significant word multiply
class T2SMMUL<bits<4> op7_4, string opc, list<dag> pattern> def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
: T2ThreeReg<(outs rGPR:$Rd), "smmul", "\t$Rd, $Rn, $Rm",
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
opc, "\t$Rd, $Rn, $Rm", pattern>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101; let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-4} = op7_4; let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMUL : T2SMMUL<0b0000, "smmul", [(set rGPR:$Rd, (mulhs rGPR:$Rn,
rGPR:$Rm))]>;
def t2SMMULR : T2SMMUL<0b0001, "smmulr", []>;
class T2FourRegSMMLA<bits<3> op22_20, bits<4> op7_4, string opc,
list<dag> pattern>
: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = op22_20;
let Inst{7-4} = op7_4;
} }
def t2SMMLA : T2FourRegSMMLA<0b101, 0b0000, "smmla", def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
[(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>; "smmulr", "\t$Rd, $Rn, $Rm", []>,
def t2SMMLAR: T2FourRegSMMLA<0b101, 0b0001, "smmlar", []>;
def t2SMMLS: T2FourRegSMMLA<0b110, 0b0000, "smmls",
[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>;
def t2SMMLSR:T2FourRegSMMLA<0b110, 0b0001, "smmlsr", []>;
class T2ThreeRegSMUL<bits<3> op22_20, bits<2> op5_4, string opc,
list<dag> pattern>
: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, opc,
"\t$Rd, $Rn, $Rm", pattern>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = op22_20; let Inst{22-20} = 0b101;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00; let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
let Inst{5-4} = op5_4;
} }
def t2SMULBB : T2ThreeRegSMUL<0b001, 0b00, "smulbb", def t2SMMLA : T2FourReg<
[(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
(sext_inreg rGPR:$Rm, i16)))]>; "smmla", "\t$Rd, $Rn, $Rm, $Ra",
def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt", [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
[(set rGPR:$Rd, (mul (sext_inreg rGPR:$Rn, i16), Requires<[IsThumb2, HasDSP, UseMulOps]> {
(sra rGPR:$Rm, (i32 16))))]>; let Inst{31-27} = 0b11111;
def t2SMULTB : T2ThreeRegSMUL<0b001, 0b10, "smultb", let Inst{26-23} = 0b0110;
[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)), let Inst{22-20} = 0b101;
(sext_inreg rGPR:$Rm, i16)))]>; let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt", }
[(set rGPR:$Rd, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16))))]>;
def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern> def t2SMMLAR: T2FourReg<
: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b101;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
def t2SMMLS: T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmls", "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0)
}
def t2SMMLSR:T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
"smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b110;
let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1)
}
multiclass T2I_smul<string opc, SDNode opnode> {
def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
(sext_inreg rGPR:$Rm, i16)))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sext_inreg rGPR:$Rm, i16)))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b10;
}
def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
[(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16))))]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
}
def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
[]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
[]>,
Requires<[IsThumb2, HasDSP]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate)
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
}
multiclass T2I_smla<string opc, SDNode opnode> {
def BB : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add rGPR:$Ra,
(opnode (sext_inreg rGPR:$Rn, i16),
(sext_inreg rGPR:$Rm, i16))))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> { Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001; let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = op5_4; let Inst{5-4} = 0b00;
} }
def t2SMLABB : T2FourRegSMLA<0b00, "smlabb", def BT : T2FourReg<
[(set rGPR:$Rd, (add rGPR:$Ra, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
(mul (sext_inreg rGPR:$Rn, i16), !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
(sext_inreg rGPR:$Rm, i16))))]>; [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
def t2SMLABT : T2FourRegSMLA<0b01, "smlabt", (sra rGPR:$Rm, (i32 16)))))]>,
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16), Requires<[IsThumb2, HasDSP, UseMulOps]> {
(sra rGPR:$Rm, (i32 16)))))]>; let Inst{31-27} = 0b11111;
def t2SMLATB : T2FourRegSMLA<0b10, "smlatb", let Inst{26-23} = 0b0110;
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), let Inst{22-20} = 0b001;
(sext_inreg rGPR:$Rm, i16))))]>; let Inst{7-6} = 0b00;
def t2SMLATT : T2FourRegSMLA<0b11, "smlatt", let Inst{5-4} = 0b01;
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>;
def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> {
let Inst{22-20} = 0b011;
}
def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
let Inst{22-20} = 0b011;
} }
class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern> def TB : T2FourReg<
: T2FourReg_mac<1, op22_20, op7_4, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
(outs rGPR:$Ra, rGPR:$Rd), !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
(ins rGPR:$Rn, rGPR:$Rm), [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>, (sext_inreg rGPR:$Rm, i16))))]>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b10;
}
def TT : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
[(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b11;
}
def WB : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b00;
}
def WT : T2FourReg<
(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
!strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
[]>,
Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b011;
let Inst{7-6} = 0b00;
let Inst{5-4} = 0b01;
}
}
defm t2SMUL : T2I_smul<"smul", mul>;
defm t2SMLA : T2I_smla<"smla", mul>;
// Halfword multiple accumulate long: SMLAL<x><y> // Halfword multiple accumulate long: SMLAL<x><y>
def t2SMLALBB : T2SMLAL<0b100, 0b1000, "smlalbb", []>; def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
def t2SMLALBT : T2SMLAL<0b100, 0b1001, "smlalbt", []>; (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
def t2SMLALTB : T2SMLAL<0b100, 0b1010, "smlaltb", []>; [/* For disassembly only; pattern left blank */]>,
def t2SMLALTT : T2SMLAL<0b100, 0b1011, "smlaltt", []>; Requires<[IsThumb2, HasDSP]>;
def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
[/* For disassembly only; pattern left blank */]>,
Requires<[IsThumb2, HasDSP]>;
class T2DualHalfMul<bits<3> op22_20, bits<4> op7_4, string opc> // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
: T2ThreeReg_mac<0, op22_20, op7_4, def t2SMUAD: T2ThreeReg_mac<
(outs rGPR:$Rd), 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> { Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111; let Inst{15-12} = 0b1111;
} }
def t2SMUADX:T2ThreeReg_mac<
// Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
def t2SMUAD: T2DualHalfMul<0b010, 0b0000, "smuad">; IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
def t2SMUADX: T2DualHalfMul<0b010, 0b0001, "smuadx">; Requires<[IsThumb2, HasDSP]> {
def t2SMUSD: T2DualHalfMul<0b100, 0b0000, "smusd">; let Inst{15-12} = 0b1111;
def t2SMUSDX: T2DualHalfMul<0b100, 0b0001, "smusdx">; }
def t2SMUSD: T2ThreeReg_mac<
class T2DualHalfMulAdd<bits<3> op22_20, bits<4> op7_4, string opc> 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
: T2FourReg_mac<0, op22_20, op7_4, IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
(outs rGPR:$Rd), Requires<[IsThumb2, HasDSP]> {
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), let Inst{15-12} = 0b1111;
IIC_iMAC32, opc, "\t$Rd, $Rn, $Rm, $Ra", []>, }
def t2SMUSDX:T2ThreeReg_mac<
0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]> {
let Inst{15-12} = 0b1111;
}
def t2SMLAD : T2FourReg_mac<
0, 0b010, 0b0000, (outs rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
def t2SMLADX : T2FourReg_mac<
def t2SMLAD : T2DualHalfMulAdd<0b010, 0b0000, "smlad">; 0, 0b010, 0b0001, (outs rGPR:$Rd),
def t2SMLADX : T2DualHalfMulAdd<0b010, 0b0001, "smladx">; (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
def t2SMLSD : T2DualHalfMulAdd<0b100, 0b0000, "smlsd">; "\t$Rd, $Rn, $Rm, $Ra", []>,
def t2SMLSDX : T2DualHalfMulAdd<0b100, 0b0001, "smlsdx">; Requires<[IsThumb2, HasDSP]>;
def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
class T2DualHalfMulAddLong<bits<3> op22_20, bits<4> op7_4, string opc> (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
: T2FourReg_mac<1, op22_20, op7_4, "\t$Rd, $Rn, $Rm, $Ra", []>,
(outs rGPR:$Ra, rGPR:$Rd), Requires<[IsThumb2, HasDSP]>;
(ins rGPR:$Rn, rGPR:$Rm), def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
IIC_iMAC64, opc, "\t$Ra, $Rd, $Rn, $Rm", []>, (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
"\t$Rd, $Rn, $Rm, $Ra", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>;
def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
(ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
"\t$Ra, $Rd, $Rn, $Rm", []>,
Requires<[IsThumb2, HasDSP]>; Requires<[IsThumb2, HasDSP]>;
def t2SMLALD : T2DualHalfMulAddLong<0b100, 0b1100, "smlald">;
def t2SMLALDX : T2DualHalfMulAddLong<0b100, 0b1101, "smlaldx">;
def t2SMLSLD : T2DualHalfMulAddLong<0b101, 0b1100, "smlsld">;
def t2SMLSLDX : T2DualHalfMulAddLong<0b101, 0b1101, "smlsldx">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Division Instructions. // Division Instructions.