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[AMDGPU] Assembler: Fix parsing error with floating-point literals passed to integer instructions 

Differential Revision: http://reviews.llvm.org/D21972

llvm-svn: 274551
This commit is contained in:
Sam Kolton 2016-07-05 14:01:11 +00:00
parent 4e96fbf3c1
commit a9cd6aa895
3 changed files with 19 additions and 6 deletions
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7
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -1107,12 +1107,6 @@ AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
return Res;
}
AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
if (Op.isImm() && Op.Imm.IsFPImm) {
Error(Parser.getTok().getLoc(), "floating point operands not allowed with sext() modifier");
return MatchOperand_ParseFail;
}
AMDGPUOperand::Modifiers Mods = {false, false, false};
if (Sext) {
if (getLexer().isNot(AsmToken::RParen)) {
@ -1124,6 +1118,7 @@ AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) {
}
if (Mods.hasIntModifiers()) {
AMDGPUOperand &Op = static_cast<AMDGPUOperand &>(*Operands.back());
Op.setModifiers(Mods);
}
return MatchOperand_Success;

10
llvm/test/MC/AMDGPU/vop1.s
View File

@ -374,3 +374,13 @@ v_sin_f16 v1, v2
// NOSICI: v_cos_f16 v1, v2
// VI: v_cos_f16_e32 v1, v2 ; encoding: [0x02,0x95,0x02,0x7e]
v_cos_f16 v1, v2
//===----------------------------------------------------------------------===//
// Floating point literals
//===----------------------------------------------------------------------===//
// GCN: v_mov_b32_e32 v0, 0.5 ; encoding: [0xf0,0x02,0x00,0x7e]
v_mov_b32 v0, 0.5
// GCN: v_mov_b32_e32 v0, 0x40480000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x00,0x48,0x40]
v_mov_b32 v0, 3.125

8
llvm/test/MC/AMDGPU/vop2.s
View File

@ -94,6 +94,14 @@ v_mul_i32_i24 v1, s2, 3
// SICI: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
v_mul_i32_i24 v1, 3, s3
// SICI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x4a]
// VI: v_add_i32_e32 v0, vcc, 0.5, v0 ; encoding: [0xf0,0x00,0x00,0x32]
v_add_i32 v0, vcc, 0.5, v0
// SICI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x4a,0x00,0x00,0x48,0x40]
// VI: v_add_i32_e32 v0, vcc, 0x40480000, v0 ; encoding: [0xff,0x00,0x00,0x32,0x00,0x00,0x48,0x40]
v_add_i32 v0, vcc, 3.125, v0
//===----------------------------------------------------------------------===//
// Instructions
//===----------------------------------------------------------------------===//