forked from OSchip/llvm-project
parent
24bfb51416
commit
aa43d0b182
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@ -126,12 +126,20 @@ let isReturn = 1, isTerminator = 1 in {
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def RET : Pseudo<(outs), (ins), "ret", [(MSP430retflag)]>;
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}
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let isBranch = 1, isTerminator = 1 in {
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// Direct branch
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let isBarrier = 1 in
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def JMP : Pseudo<(outs), (ins brtarget:$dst),
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"jmp\t$dst",
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[(br bb:$dst)]>;
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// Conditional branches
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let isBranch = 1, isTerminator = 1, Uses = [SRW] in {
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def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
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"j$cc $dst",
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[(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
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} // Uses = [SRW]
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let Uses = [SRW] in
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def JCC : Pseudo<(outs), (ins brtarget:$dst, cc:$cc),
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"j$cc $dst",
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[(MSP430brcond bb:$dst, imm:$cc, SRW)]>;
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} // isBranch, isTerminator
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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