forked from OSchip/llvm-project
parent
fe1202c4cb
commit
ae7c97d39d
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@ -73,8 +73,8 @@ static void tieOpsIfNeeded(MachineInstr &MI) {
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// MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
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// are the halfword immediate loads for the same word. Try to use one of them
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// instead of IIxF.
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bool SystemZShortenInst::shortenIIF(MachineInstr &MI,
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unsigned LLIxL, unsigned LLIxH) {
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bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned LLIxL,
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unsigned LLIxH) {
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unsigned Reg = MI.getOperand(0).getReg();
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// The new opcode will clear the other half of the GR64 reg, so
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// cancel if that is live.
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