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[RISCV] Add patterns for scalable-vector fsqrt 

This patch adds support for lowering the sqrt intrinsic to the RVV
vfsqrt instruction.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D96012
This commit is contained in:
Fraser Cormack 2021-02-04 11:13:45 +00:00
parent 502a67dd7f
commit af48d2bfc2
2 changed files with 192 additions and 2 deletions
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9
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
View File

@ -585,9 +585,14 @@ foreach fvti = AllFloatVectors in {
fvti.AVL, fvti.SEW)>; fvti.AVL, fvti.SEW)>;
} }
// 14.10. Vector Floating-Point Sign-Injection Instructions
// Handle fneg with VFSGNJN using the same input for both operands.
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
// 14.8. Vector Floating-Point Square-Root Instruction
def : Pat<(fsqrt (vti.Vector vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX)
vti.RegClass:$rs2, vti.AVL, vti.SEW)>;
// 14.10. Vector Floating-Point Sign-Injection Instructions
// Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)), def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.SEW)>; vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.SEW)>;

185
llvm/test/CodeGen/RISCV/rvv/vfsqrt-sdnode.ll Normal file
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@ -0,0 +1,185 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.sqrt.nxv1f16(<vscale x 1 x half>)
define <vscale x 1 x half> @vfsqrt_nxv1f16(<vscale x 1 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 1 x half> @llvm.sqrt.nxv1f16(<vscale x 1 x half> %v)
ret <vscale x 1 x half> %r
}
declare <vscale x 2 x half> @llvm.sqrt.nxv2f16(<vscale x 2 x half>)
define <vscale x 2 x half> @vfsqrt_nxv2f16(<vscale x 2 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 2 x half> @llvm.sqrt.nxv2f16(<vscale x 2 x half> %v)
ret <vscale x 2 x half> %r
}
declare <vscale x 4 x half> @llvm.sqrt.nxv4f16(<vscale x 4 x half>)
define <vscale x 4 x half> @vfsqrt_nxv4f16(<vscale x 4 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 4 x half> @llvm.sqrt.nxv4f16(<vscale x 4 x half> %v)
ret <vscale x 4 x half> %r
}
declare <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half>)
define <vscale x 8 x half> @vfsqrt_nxv8f16(<vscale x 8 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv8f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half> %v)
ret <vscale x 8 x half> %r
}
declare <vscale x 16 x half> @llvm.sqrt.nxv16f16(<vscale x 16 x half>)
define <vscale x 16 x half> @vfsqrt_nxv16f16(<vscale x 16 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv16f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 16 x half> @llvm.sqrt.nxv16f16(<vscale x 16 x half> %v)
ret <vscale x 16 x half> %r
}
declare <vscale x 32 x half> @llvm.sqrt.nxv32f16(<vscale x 32 x half>)
define <vscale x 32 x half> @vfsqrt_nxv32f16(<vscale x 32 x half> %v) {
; CHECK-LABEL: vfsqrt_nxv32f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 32 x half> @llvm.sqrt.nxv32f16(<vscale x 32 x half> %v)
ret <vscale x 32 x half> %r
}
declare <vscale x 1 x float> @llvm.sqrt.nxv1f32(<vscale x 1 x float>)
define <vscale x 1 x float> @vfsqrt_nxv1f32(<vscale x 1 x float> %v) {
; CHECK-LABEL: vfsqrt_nxv1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 1 x float> @llvm.sqrt.nxv1f32(<vscale x 1 x float> %v)
ret <vscale x 1 x float> %r
}
declare <vscale x 2 x float> @llvm.sqrt.nxv2f32(<vscale x 2 x float>)
define <vscale x 2 x float> @vfsqrt_nxv2f32(<vscale x 2 x float> %v) {
; CHECK-LABEL: vfsqrt_nxv2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 2 x float> @llvm.sqrt.nxv2f32(<vscale x 2 x float> %v)
ret <vscale x 2 x float> %r
}
declare <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float>)
define <vscale x 4 x float> @vfsqrt_nxv4f32(<vscale x 4 x float> %v) {
; CHECK-LABEL: vfsqrt_nxv4f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float> %v)
ret <vscale x 4 x float> %r
}
declare <vscale x 8 x float> @llvm.sqrt.nxv8f32(<vscale x 8 x float>)
define <vscale x 8 x float> @vfsqrt_nxv8f32(<vscale x 8 x float> %v) {
; CHECK-LABEL: vfsqrt_nxv8f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 8 x float> @llvm.sqrt.nxv8f32(<vscale x 8 x float> %v)
ret <vscale x 8 x float> %r
}
declare <vscale x 16 x float> @llvm.sqrt.nxv16f32(<vscale x 16 x float>)
define <vscale x 16 x float> @vfsqrt_nxv16f32(<vscale x 16 x float> %v) {
; CHECK-LABEL: vfsqrt_nxv16f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 16 x float> @llvm.sqrt.nxv16f32(<vscale x 16 x float> %v)
ret <vscale x 16 x float> %r
}
declare <vscale x 1 x double> @llvm.sqrt.nxv1f64(<vscale x 1 x double>)
define <vscale x 1 x double> @vfsqrt_nxv1f64(<vscale x 1 x double> %v) {
; CHECK-LABEL: vfsqrt_nxv1f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 1 x double> @llvm.sqrt.nxv1f64(<vscale x 1 x double> %v)
ret <vscale x 1 x double> %r
}
declare <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double>)
define <vscale x 2 x double> @vfsqrt_nxv2f64(<vscale x 2 x double> %v) {
; CHECK-LABEL: vfsqrt_nxv2f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double> %v)
ret <vscale x 2 x double> %r
}
declare <vscale x 4 x double> @llvm.sqrt.nxv4f64(<vscale x 4 x double>)
define <vscale x 4 x double> @vfsqrt_nxv4f64(<vscale x 4 x double> %v) {
; CHECK-LABEL: vfsqrt_nxv4f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 4 x double> @llvm.sqrt.nxv4f64(<vscale x 4 x double> %v)
ret <vscale x 4 x double> %r
}
declare <vscale x 8 x double> @llvm.sqrt.nxv8f64(<vscale x 8 x double>)
define <vscale x 8 x double> @vfsqrt_nxv8f64(<vscale x 8 x double> %v) {
; CHECK-LABEL: vfsqrt_nxv8f64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vfsqrt.v v8, v8
; CHECK-NEXT: ret
%r = call <vscale x 8 x double> @llvm.sqrt.nxv8f64(<vscale x 8 x double> %v)
ret <vscale x 8 x double> %r
}