forked from OSchip/llvm-project
parent
2a341620e7
commit
aff09bf052
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@ -4216,26 +4216,36 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
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/// \brief Replace csincr-branch sequence by simple conditional branch
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///
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/// Examples:
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/// 1.
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/// 1. \code
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/// csinc w9, wzr, wzr, <condition code>
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/// tbnz w9, #0, 0x44
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/// \endcode
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/// to
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/// \code
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/// b.<inverted condition code>
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/// \endcode
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///
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/// 2.
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/// 2. \code
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/// csinc w9, wzr, wzr, <condition code>
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/// tbz w9, #0, 0x44
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/// \endcode
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/// to
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/// \code
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/// b.<condition code>
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/// \endcode
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///
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/// Replace compare and branch sequence by TBZ/TBNZ instruction when the
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/// compare's constant operand is power of 2.
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///
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/// Examples:
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/// \code
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/// and w8, w8, #0x400
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/// cbnz w8, L1
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/// \endcode
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/// to
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/// \code
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/// tbnz w8, #10, L1
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/// \endcode
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///
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/// \param MI Conditional Branch
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/// \return True when the simple conditional branch is generated
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