forked from OSchip/llvm-project
[AMDGPU] Divergence driven instruction selection. Shift operations.
Summary: This change enables VOP3 shifts to be explicitly selected
dependent on the divergence.
Differential Revision: https://reviews.llvm.org/D52559
Reviewers: rampitec
llvm-svn: 343455
This commit is contained in:
Alexander Timofeev
parent
06e65cae4a
commit
b048fa3344
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@ -442,19 +442,19 @@ def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
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[(set i32:$sdst, (UniformBinFrag<shl> i32:$src0, i32:$src1))]
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>;
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def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
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[(set i64:$sdst, (shl i64:$src0, i32:$src1))]
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[(set i64:$sdst, (UniformBinFrag<shl> i64:$src0, i32:$src1))]
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>;
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def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
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[(set i32:$sdst, (UniformBinFrag<srl> i32:$src0, i32:$src1))]
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>;
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def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
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[(set i64:$sdst, (srl i64:$src0, i32:$src1))]
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[(set i64:$sdst, (UniformBinFrag<srl> i64:$src0, i32:$src1))]
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>;
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def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
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[(set i32:$sdst, (UniformBinFrag<sra> i32:$src0, i32:$src1))]
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>;
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def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
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[(set i64:$sdst, (sra i64:$src0, i32:$src1))]
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[(set i64:$sdst, (UniformBinFrag<sra> i64:$src0, i32:$src1))]
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>;
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} // End Defs = [SCC]
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@ -17,16 +17,16 @@ class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
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(VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
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list<dag> ret3 = [(set P.DstVT:$vdst,
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(node (P.Src0VT src0),
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(DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
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list<dag> ret2 = [(set P.DstVT:$vdst,
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(node (P.Src0VT src0),
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(DivergentFragOrOp<node, P>.ret (P.Src0VT src0),
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(P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
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list<dag> ret1 = [(set P.DstVT:$vdst,
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(node (P.Src0VT src0)))];
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(DivergentFragOrOp<node, P>.ret (P.Src0VT src0)))];
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list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
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!if(!eq(P.NumSrcArgs, 2), ret2,
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@ -35,18 +35,18 @@ class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
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class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
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list<dag> ret3 = [(set P.DstVT:$vdst,
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(node (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
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list<dag> ret2 = [(set P.DstVT:$vdst,
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(node !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
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list<dag> ret1 = [(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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(DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
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!if(!eq(P.NumSrcArgs, 2), ret2,
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@ -55,18 +55,18 @@ class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
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class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
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list<dag> ret3 = [(set P.DstVT:$vdst,
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(node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
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list<dag> ret2 = [(set P.DstVT:$vdst,
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(node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
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list<dag> ret1 = [(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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(DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
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!if(!eq(P.NumSrcArgs, 2), ret2,
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@ -75,18 +75,18 @@ class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
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class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
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list<dag> ret3 = [(set P.DstVT:$vdst,
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(node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(DivergentFragOrOp<node, P>.ret (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
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(VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
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(P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
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list<dag> ret2 = [(set P.DstVT:$vdst,
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(node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(DivergentFragOrOp<node, P>.ret !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
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(P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
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(P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
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list<dag> ret1 = [(set P.DstVT:$vdst,
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(node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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(DivergentFragOrOp<node, P>.ret (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
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list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
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!if(!eq(P.NumSrcArgs, 2), ret2,
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@ -94,9 +94,9 @@ class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
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}
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class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
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list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
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list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
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list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
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list<dag> ret3 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
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list<dag> ret2 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0, P.Src1VT:$src1))];
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list<dag> ret1 = [(set P.DstVT:$vdst, (DivergentFragOrOp<node, P>.ret P.Src0VT:$src0))];
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list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
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!if(!eq(P.NumSrcArgs, 2), ret2,
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ret1));
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@ -185,6 +185,7 @@ class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProf
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getAsm64<HasDst, NumSrcArgs, HasIntClamp,
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HasModifiers, HasOMod, DstVT>.ret,
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P.Asm64));
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let NeedPatGen = P.NeedPatGen;
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}
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class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
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@ -381,12 +382,12 @@ def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I3
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let SchedRW = [Write64Bit] in {
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// These instructions only exist on SI and CI
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let SubtargetPredicate = isSICI in {
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def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
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def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
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def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
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let SubtargetPredicate = isSICI, Predicates = [isSICI] in {
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def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, shl>;
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def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, srl>;
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def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_PAT_GEN<VOP_I64_I64_I32>>, sra>;
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def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
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} // End SubtargetPredicate = isSICI
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} // End SubtargetPredicate = isSICI, Predicates = [isSICI]
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let SubtargetPredicate = isVI in {
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def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
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@ -395,6 +396,22 @@ def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
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} // End SubtargetPredicate = isVI
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} // End SchedRW = [Write64Bit]
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let Predicates = [isVI] in {
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def : GCNPat <
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(getDivergentFrag<shl>.ret i64:$x, i32:$y),
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(V_LSHLREV_B64 $y, $x)
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>;
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def : AMDGPUPat <
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(getDivergentFrag<srl>.ret i64:$x, i32:$y),
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(V_LSHRREV_B64 $y, $x)
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>;
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def : AMDGPUPat <
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(getDivergentFrag<sra>.ret i64:$x, i32:$y),
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(V_ASHRREV_I64 $y, $x)
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>;
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}
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let SubtargetPredicate = isCIVI in {
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let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
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@ -572,6 +572,11 @@ class VOPPatOrNull<SDPatternOperator Op, VOPProfile P> {
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list<dag> ret = !if(!ne(P.NeedPatGen,PatGenMode.NoPattern), VOPPatGen<Op, P>.ret, []);
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}
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class DivergentFragOrOp<SDPatternOperator Op, VOPProfile P> {
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SDPatternOperator ret = !if(!eq(P.NeedPatGen,PatGenMode.Pattern),
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!if(!isa<SDNode>(Op), getDivergentFrag<Op>.ret, Op), Op);
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}
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include "VOPCInstructions.td"
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include "VOP1Instructions.td"
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include "VOP2Instructions.td"
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