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[AMDGPU] Return true in enableMultipleCopyHints(). 

Enable multiple COPY hints to eliminate more COPYs during register allocation.

Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.

Review: Stanislav Mekhanoshin, Tom Stellard.
llvm-svn: 325425
This commit is contained in:
Jonas Paulsson 2018-02-17 10:00:28 +00:00
parent b0e4f87fb0
commit b51a9bc358
4 changed files with 14 additions and 12 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPURegisterInfo.h
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@ -27,6 +27,8 @@ class TargetInstrInfo;
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo { struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
AMDGPURegisterInfo(); AMDGPURegisterInfo();
bool enableMultipleCopyHints() const override { return true; }
/// \returns the sub reg enum value for the given \p Channel /// \returns the sub reg enum value for the given \p Channel
/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
unsigned getSubRegFromChannel(unsigned Channel) const; unsigned getSubRegFromChannel(unsigned Channel) const;

12
llvm/test/CodeGen/AMDGPU/callee-special-input-sgprs.ll
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@ -208,8 +208,8 @@ define amdgpu_kernel void @kern_indirect_use_workgroup_id_x() #1 {
; GCN: enable_sgpr_workgroup_id_z = 0 ; GCN: enable_sgpr_workgroup_id_z = 0
; GCN: s_mov_b32 s33, s8 ; GCN: s_mov_b32 s33, s8
; GCN: s_mov_b32 s4, s33 ; GCN-DAG: s_mov_b32 s4, s33
; GCN: s_mov_b32 s6, s7 ; GCN-DAG: s_mov_b32 s6, s7
; GCN: s_mov_b32 s32, s33 ; GCN: s_mov_b32 s32, s33
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_indirect_use_workgroup_id_y() #1 { define amdgpu_kernel void @kern_indirect_use_workgroup_id_y() #1 {
@ -223,8 +223,8 @@ define amdgpu_kernel void @kern_indirect_use_workgroup_id_y() #1 {
; GCN: enable_sgpr_workgroup_id_z = 1 ; GCN: enable_sgpr_workgroup_id_z = 1
; GCN: s_mov_b32 s33, s8 ; GCN: s_mov_b32 s33, s8
; GCN: s_mov_b32 s4, s33 ; GCN-DAG: s_mov_b32 s4, s33
; GCN: s_mov_b32 s6, s7 ; GCN-DAG: s_mov_b32 s6, s7
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_indirect_use_workgroup_id_z() #1 { define amdgpu_kernel void @kern_indirect_use_workgroup_id_z() #1 {
call void @use_workgroup_id_z() call void @use_workgroup_id_z()
@ -396,7 +396,7 @@ define amdgpu_kernel void @kern_indirect_other_arg_use_workgroup_id_x() #1 {
; GCN-DAG: s_mov_b32 s33, s8 ; GCN-DAG: s_mov_b32 s33, s8
; GCN-DAG: v_mov_b32_e32 v0, 0x22b ; GCN-DAG: v_mov_b32_e32 v0, 0x22b
; GCN: s_mov_b32 s4, s33 ; GCN-DAG: s_mov_b32 s4, s33
; GCN-DAG: s_mov_b32 s6, s7 ; GCN-DAG: s_mov_b32 s6, s7
; GCN-DAG: s_mov_b32 s32, s33 ; GCN-DAG: s_mov_b32 s32, s33
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
@ -412,7 +412,7 @@ define amdgpu_kernel void @kern_indirect_other_arg_use_workgroup_id_y() #1 {
; GCN: s_mov_b32 s33, s8 ; GCN: s_mov_b32 s33, s8
; GCN-DAG: v_mov_b32_e32 v0, 0x22b ; GCN-DAG: v_mov_b32_e32 v0, 0x22b
; GCN: s_mov_b32 s4, s33 ; GCN-DAG: s_mov_b32 s4, s33
; GCN-DAG: s_mov_b32 s6, s7 ; GCN-DAG: s_mov_b32 s6, s7
; GCN: s_mov_b32 s32, s33 ; GCN: s_mov_b32 s32, s33

4
llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
View File

@ -220,8 +220,8 @@ define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_y() #1 {
; GCN-LABEL: {{^}}kern_indirect_other_arg_use_workitem_id_z: ; GCN-LABEL: {{^}}kern_indirect_other_arg_use_workitem_id_z:
; GCN: enable_vgpr_workitem_id = 2 ; GCN: enable_vgpr_workitem_id = 2
; GCN: v_mov_b32_e32 v0, 0x22b ; GCN-DAG: v_mov_b32_e32 v0, 0x22b
; GCN: v_mov_b32_e32 v1, v2 ; GCN-DAG: v_mov_b32_e32 v1, v2
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NOT: v0 ; GCN-NOT: v0
define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_z() #1 { define amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_z() #1 {

8
llvm/test/CodeGen/AMDGPU/ret.ll
View File

@ -126,9 +126,9 @@ bb:
; GCN-LABEL: {{^}}vgpr_ps_addr119: ; GCN-LABEL: {{^}}vgpr_ps_addr119:
; GCN-DAG: v_mov_b32_e32 v0, v2 ; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3 ; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mov_b32_e32 v2, v6 ; GCN-DAG: v_mov_b32_e32 v2, v6
; GCN: v_mov_b32_e32 v3, v8 ; GCN-DAG: v_mov_b32_e32 v3, v8
; GCN: v_mov_b32_e32 v4, v12 ; GCN-DAG: v_mov_b32_e32 v4, v12
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 { define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 {
bb: bb:
@ -178,8 +178,8 @@ bb:
} }
; GCN-LABEL: {{^}}sgpr: ; GCN-LABEL: {{^}}sgpr:
; GCN: s_add_i32 s0, s3, 2
; GCN: s_mov_b32 s2, s3 ; GCN: s_mov_b32 s2, s3
; GCN: s_add_i32 s0, s2, 2
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb: