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[mips] Fix predicates of mfc1, mtc1 instructions 

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46692

llvm-svn: 332339
This commit is contained in:
Simon Dardis 2018-05-15 11:10:30 +00:00
parent 761c2247b4
commit b79ecec20d
7 changed files with 46 additions and 28 deletions
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17
llvm/lib/Target/Mips/MicroMipsInstrFPU.td
View File

@ -187,17 +187,14 @@ let DecoderNamespace = "MicroMips" in {
def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
}
let isCodeGenOnly = 1 in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS;
}
let DecoderNamespace = "MicroMips" in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS;
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,

33
llvm/lib/Target/Mips/MipsInstrFPU.td
View File

@ -478,37 +478,34 @@ let AdditionalPredicates = [NotInMicroMips] in {
let AdditionalPredicates = [NotInMicroMips] in {
def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>;
def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>;
}
def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
bitconvert>, MFC1_FM<0>;
def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
FGR_64 {
let DecoderNamespace = "MipsFP64";
}
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
bitconvert>, MFC1_FM<4>;
def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
FGR_64 {
let DecoderNamespace = "MipsFP64";
}
let AdditionalPredicates = [NotInMicroMips] in {
def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
bitconvert>, MFC1_FM<0>;
def MFC1_D64 : MFC1_FT<"mfc1", GPR32Opnd, FGR64Opnd, II_MFC1>, MFC1_FM<0>,
FGR_64 {
let DecoderNamespace = "MipsFP64";
}
def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
bitconvert>, MFC1_FM<4>;
def MTC1_D64 : MTC1_FT<"mtc1", FGR64Opnd, GPR32Opnd, II_MTC1>, MFC1_FM<4>,
FGR_64 {
let DecoderNamespace = "MipsFP64";
}
def MFHC1_D32 : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_32;
def MFHC1_D64 : MFC1_FT<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>,
MFC1_FM<3>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
}
let AdditionalPredicates = [NotInMicroMips] in {
def MTHC1_D32 : MMRel, StdMMR6Rel, MTC1_64_FT<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_32;
def MTHC1_D64 : MTC1_64_FT<"mthc1", FGR64Opnd, GPR32Opnd, II_MTHC1>,
MFC1_FM<7>, ISA_MIPS32R2, FGR_64 {
let DecoderNamespace = "MipsFP64";
}
}
let AdditionalPredicates = [NotInMicroMips] in {
def DMTC1 : MTC1_FT<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1,
bitconvert>, MFC1_FM<5>, ISA_MIPS3;
def DMFC1 : MFC1_FT<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1,

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
View File

@ -252,3 +252,7 @@
0xc8 0x54 0x3b 0x7b # CHECK: round.w.d $f6, $f8
0xc8 0x54 0x3b 0x2b # CHECK: trunc.w.s $f6, $f8
0xc8 0x54 0x3b 0x6b # CHECK: trunc.w.d $f6, $f8
0x86 0x54 0x3b 0x28 # CHECK: mtc1 $4, $f6
0x86 0x54 0x3b 0x20 # CHECK: mfc1 $4, $f6
0x86 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f6
0x86 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f6

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64-el.txt
View File

@ -21,3 +21,7 @@
0x82 0x54 0x3b 0x41 # CHECK: cvt.l.d $f4, $f2
0x85 0x54 0x48 0x21 # CHECK: luxc1 $f4, $4($5)
0x85 0x54 0x88 0x21 # CHECK: suxc1 $f4, $4($5)
0x86 0x54 0x3b 0x28 # CHECK: mtc1 $4, $f6
0x86 0x54 0x3b 0x20 # CHECK: mfc1 $4, $f6
0x86 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f6
0x86 0x54 0x3b 0x30 # CHECK: mfhc1 $4, $f6

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-fp64.txt
View File

@ -21,3 +21,7 @@
0x54 0x82 0x41 0x3b # CHECK: cvt.l.d $f4, $f2
0x54 0x85 0x21 0x48 # CHECK: luxc1 $f4, $4($5)
0x54 0x85 0x21 0x88 # CHECK: suxc1 $f4, $4($5)
0x54 0x86 0x28 0x3b # CHECK: mtc1 $4, $f6
0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6

4
llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
View File

@ -254,3 +254,7 @@
0x54 0xc8 0x7b 0x3b # CHECK: round.w.d $f6, $f8
0x54 0xc8 0x2b 0x3b # CHECK: trunc.w.s $f6, $f8
0x54 0xc8 0x6b 0x3b # CHECK: trunc.w.d $f6, $f8
0x54 0x86 0x28 0x3b # CHECK: mtc1 $4, $f6
0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6

8
llvm/test/MC/Mips/micromips-fpu-instructions.s
View File

@ -62,9 +62,13 @@
# CHECK-EL: cfc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x10]
# CHECK-EL: ctc1 $6, $0 # encoding: [0xc0,0x54,0x3b,0x18]
# CHECK-EL: mfc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MFC1_MM
# CHECK-EL: mtc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x28]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MTC1_MM
# CHECK-EL: mfhc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x30]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
# CHECK-EL: mthc1 $6, $f8 # encoding: [0xc8,0x54,0x3b,0x38]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
# CHECK-EL: movz.s $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x20]
# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EL: movz.d $f4, $f6, $7 # encoding: [0xe6,0x54,0x78,0x21]
@ -145,9 +149,13 @@
# CHECK-EB: cfc1 $6, $0 # encoding: [0x54,0xc0,0x10,0x3b]
# CHECK-EB: ctc1 $6, $0 # encoding: [0x54,0xc0,0x18,0x3b]
# CHECK-EB: mfc1 $6, $f8 # encoding: [0x54,0xc8,0x20,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MFC1_MM
# CHECK-EB: mtc1 $6, $f8 # encoding: [0x54,0xc8,0x28,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MTC1_MM
# CHECK-EB: mfhc1 $6, $f8 # encoding: [0x54,0xc8,0x30,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MFHC1_D32_MM
# CHECK-EB: mthc1 $6, $f8 # encoding: [0x54,0xc8,0x38,0x3b]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MTHC1_D32_MM
# CHECK-EB: movz.s $f4, $f6, $7 # encoding: [0x54,0xe6,0x20,0x78]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVZ_I_S_MM
# CHECK-EB: movz.d $f4, $f6, $7 # encoding: [0x54,0xe6,0x21,0x78]