forked from OSchip/llvm-project
AMDGPU/GlobalISel: Select llvm.amdgcn.mov.dpp
This is deprecated, but easy to support.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
dd09ec1208
commit
c05f23e409
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@ -3104,6 +3104,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case Intrinsic::amdgcn_ds_bpermute:
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case Intrinsic::amdgcn_update_dpp:
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case Intrinsic::amdgcn_mov_dpp8:
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case Intrinsic::amdgcn_mov_dpp:
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return getDefaultMappingAllVGPR(MI);
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case Intrinsic::amdgcn_kernarg_segment_ptr:
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case Intrinsic::amdgcn_s_getpc:
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@ -1957,11 +1957,12 @@ def : GCNPat <
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>;
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def : GCNPat <
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(i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
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timm:$bound_ctrl)),
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(V_MOV_B64_DPP_PSEUDO $src, $src, (as_i32imm $dpp_ctrl),
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(as_i32imm $row_mask), (as_i32imm $bank_mask),
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(as_i1imm $bound_ctrl))
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(i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask,
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timm:$bank_mask, timm:$bound_ctrl)),
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(V_MOV_B64_DPP_PSEUDO VReg_64:$src, VReg_64:$src,
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(as_i32timm $dpp_ctrl), (as_i32timm $row_mask),
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(as_i32timm $bank_mask),
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(as_i1timm $bound_ctrl))
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>;
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def : GCNPat <
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@ -815,11 +815,11 @@ def V_MOV_B32_indirect : VPseudoInstSI<(outs),
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let OtherPredicates = [isGFX8Plus] in {
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def : GCNPat <
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(i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask, timm:$bank_mask,
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timm:$bound_ctrl)),
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(V_MOV_B32_dpp $src, $src, (as_i32imm $dpp_ctrl),
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(as_i32imm $row_mask), (as_i32imm $bank_mask),
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(as_i1imm $bound_ctrl))
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(i32 (int_amdgcn_mov_dpp i32:$src, timm:$dpp_ctrl, timm:$row_mask,
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timm:$bank_mask, timm:$bound_ctrl)),
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(V_MOV_B32_dpp VGPR_32:$src, VGPR_32:$src, (as_i32timm $dpp_ctrl),
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(as_i32timm $row_mask), (as_i32timm $bank_mask),
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(as_i1timm $bound_ctrl))
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>;
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def : GCNPat <
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@ -0,0 +1,72 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
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; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
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; FIXME: Merge with DAG test
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define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in) {
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; GFX8-LABEL: dpp_test:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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; GFX8-NEXT: s_load_dword s0, s[0:1], 0x2c
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: v_mov_b32_e32 v2, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: s_nop 0
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; GFX8-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX10-LABEL: dpp_test:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; encoding: [0x80,0x00,0x04,0xf4,0x24,0x00,0x00,0xfa]
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; GFX10-NEXT: s_load_dword s0, s[0:1], 0x2c ; encoding: [0x00,0x00,0x00,0xf4,0x2c,0x00,0x00,0xfa]
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
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; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; encoding: [0x02,0x02,0x00,0x7e]
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; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; encoding: [0x00,0x02,0x04,0x7e]
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; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; encoding: [0x03,0x02,0x02,0x7e]
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; GFX10-NEXT: v_mov_b32_dpp v2, v2 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x04,0x7e,0x02,0x01,0x08,0x11]
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; GFX10-NEXT: global_store_dword v[0:1], v2, off ; encoding: [0x00,0x80,0x70,0xdc,0x00,0x02,0x7d,0x00]
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; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
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%tmp0 = call i32 @llvm.amdgcn.mov.dpp.i32(i32 %in, i32 1, i32 1, i32 1, i1 true) #0
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store i32 %tmp0, i32 addrspace(1)* %out
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ret void
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}
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define amdgpu_kernel void @mov_dpp64_test(i64 addrspace(1)* %out, i64 %in1) {
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; GFX8-LABEL: mov_dpp64_test:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: v_mov_b32_e32 v3, s1
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; GFX8-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX8-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1
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; GFX8-NEXT: v_mov_b32_e32 v2, s0
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; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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; GFX8-NEXT: s_endpgm
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;
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; GFX10-LABEL: mov_dpp64_test:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; encoding: [0x00,0x00,0x08,0xf4,0x24,0x00,0x00,0xfa]
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; GFX10-NEXT: ; implicit-def: $vcc_hi
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; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
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; GFX10-NEXT: v_mov_b32_e32 v0, s2 ; encoding: [0x02,0x02,0x00,0x7e]
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; GFX10-NEXT: v_mov_b32_e32 v1, s3 ; encoding: [0x03,0x02,0x02,0x7e]
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; GFX10-NEXT: v_mov_b32_e32 v3, s1 ; encoding: [0x01,0x02,0x06,0x7e]
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; GFX10-NEXT: v_mov_b32_e32 v2, s0 ; encoding: [0x00,0x02,0x04,0x7e]
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; GFX10-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x00,0x7e,0x00,0x01,0x00,0x11]
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; GFX10-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 ; encoding: [0xfa,0x02,0x02,0x7e,0x01,0x01,0x00,0x11]
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; GFX10-NEXT: global_store_dwordx2 v[2:3], v[0:1], off ; encoding: [0x00,0x80,0x74,0xdc,0x02,0x00,0x7d,0x00]
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; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
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%tmp0 = call i64 @llvm.amdgcn.mov.dpp.i64(i64 %in1, i32 1, i32 1, i32 1, i1 false) #0
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store i64 %tmp0, i64 addrspace(1)* %out
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ret void
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}
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declare i32 @llvm.amdgcn.mov.dpp.i32(i32, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #0
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declare i64 @llvm.amdgcn.mov.dpp.i64(i64, i32 immarg, i32 immarg, i32 immarg, i1 immarg) #0
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attributes #0 = { convergent nounwind readnone }
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