forked from OSchip/llvm-project
AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsics
llvm-svn: 373840
This commit is contained in:
Matt Arsenault
parent
bcd6b1d209
commit
c0ec72d4f8
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@ -1823,6 +1823,21 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
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constrainOpWithReadfirstlane(MI, MRI, 2); // M0
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return;
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}
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier:
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case Intrinsic::amdgcn_ds_gws_sema_br: {
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// Only the first lane is executes, so readfirstlane is safe.
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substituteSimpleCopyRegs(OpdMapper, 1);
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constrainOpWithReadfirstlane(MI, MRI, 2); // M0
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return;
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}
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case Intrinsic::amdgcn_ds_gws_sema_v:
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case Intrinsic::amdgcn_ds_gws_sema_p:
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case Intrinsic::amdgcn_ds_gws_sema_release_all: {
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// Only the first lane is executes, so readfirstlane is safe.
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constrainOpWithReadfirstlane(MI, MRI, 1); // M0
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return;
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}
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case Intrinsic::amdgcn_s_sendmsg:
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case Intrinsic::amdgcn_s_sendmsghalt: {
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// FIXME: Should this use a waterfall loop?
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@ -2843,6 +2858,26 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size);
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break;
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}
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case Intrinsic::amdgcn_ds_gws_init:
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case Intrinsic::amdgcn_ds_gws_barrier:
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case Intrinsic::amdgcn_ds_gws_sema_br: {
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OpdsMapping[1] = AMDGPU::getValueMapping(AMDGPU::VGPRRegBankID, 32);
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// This must be an SGPR, but accept a VGPR.
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unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
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AMDGPU::SGPRRegBankID);
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OpdsMapping[2] = AMDGPU::getValueMapping(Bank, 32);
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break;
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}
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case Intrinsic::amdgcn_ds_gws_sema_v:
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case Intrinsic::amdgcn_ds_gws_sema_p:
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case Intrinsic::amdgcn_ds_gws_sema_release_all: {
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// This must be an SGPR, but accept a VGPR.
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unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
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AMDGPU::SGPRRegBankID);
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OpdsMapping[1] = AMDGPU::getValueMapping(Bank, 32);
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break;
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}
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default:
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if (const AMDGPU::RsrcIntrinsic *RSrcIntrin =
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AMDGPU::lookupRsrcIntrinsic(IntrID)) {
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@ -0,0 +1,79 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: ds_gws_init_s_s
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: ds_gws_init_s_s
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; CHECK: liveins: $sgpr0, $sgpr1
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), [[COPY2]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), %0, %1
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...
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---
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name: ds_gws_init_s_v
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; CHECK-LABEL: name: ds_gws_init_s_v
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; CHECK: liveins: $sgpr0, $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), [[COPY2]](s32), [[V_READFIRSTLANE_B32_]]
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%0:_(s32) = COPY $sgpr0
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%1:_(s32) = COPY $vgpr0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), %0, %1
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...
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---
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name: ds_gws_init_v_s
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; CHECK-LABEL: name: ds_gws_init_v_s
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; CHECK: liveins: $vgpr0, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), [[COPY]](s32), [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $sgpr0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), %0, %1
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...
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---
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name: ds_gws_init_v_v
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: ds_gws_init_v_v
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; CHECK: liveins: $vgpr0, $vgpr1
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]](s32), implicit $exec
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), [[COPY]](s32), [[V_READFIRSTLANE_B32_]]
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.init), %0, %1
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...
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@ -0,0 +1,37 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: ds_gws_init_s
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; CHECK-LABEL: name: ds_gws_init_s
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; CHECK: liveins: $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[COPY]](s32)
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%0:_(s32) = COPY $sgpr0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
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...
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---
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name: ds_gws_init_v
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: ds_gws_init_v
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; CHECK: liveins: $vgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
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; CHECK: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]](s32), implicit $exec
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; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), [[V_READFIRSTLANE_B32_]]
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%0:_(s32) = COPY $vgpr0
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G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.ds.gws.sema.v), %0
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...
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