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AArch64: skip select/setcc combine in complex case. 

In an llvm-stress generated test, we were trying to create a v0iN type and
asserting when that failed. This case could probably be handled by the
function, but not without added complexity and the situation it arises in is
sufficiently odd that there's probably no benefit anyway.

Should fix PR20775.

llvm-svn: 216725
This commit is contained in:
Tim Northover 2014-08-29 13:05:18 +00:00
parent 73e171f76d
commit c1c05aeb5d
2 changed files with 20 additions and 8 deletions
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18
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -7994,22 +7994,24 @@ static SDValue performVSelectCombine(SDNode *N, SelectionDAG &DAG) {
static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) { static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
SDValue N0 = N->getOperand(0); SDValue N0 = N->getOperand(0);
EVT ResVT = N->getValueType(0); EVT ResVT = N->getValueType(0);
EVT SrcVT = N0.getOperand(0).getValueType();
int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
if (!N->getOperand(1).getValueType().isVector()) // If NumMaskElts == 0, the comparison is larger than select result. The
// largest real NEON comparison is 64-bits per lane, which means the result is
// at most 32-bits and an illegal vector. Just bail out for now.
if (!ResVT.isVector() || NumMaskElts == 0)
return SDValue(); return SDValue();
if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1) if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)
return SDValue(); return SDValue();
SDLoc DL(N0); SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);
EVT SrcVT = N0.getOperand(0).getValueType();
SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,
ResVT.getSizeInBits() / SrcVT.getSizeInBits());
EVT CCVT = SrcVT.changeVectorElementTypeToInteger(); EVT CCVT = SrcVT.changeVectorElementTypeToInteger();
// First perform a vector comparison, where lane 0 is the one we're interested // First perform a vector comparison, where lane 0 is the one we're interested
// in. // in.
SDLoc DL(N0);
SDValue LHS = SDValue LHS =
DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0)); DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));
SDValue RHS = SDValue RHS =
@ -8019,8 +8021,8 @@ static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
// Now duplicate the comparison mask we want across all other lanes. // Now duplicate the comparison mask we want across all other lanes.
SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0); SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);
SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data()); SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());
Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(), Mask = DAG.getNode(ISD::BITCAST, DL,
Mask); ResVT.changeVectorElementTypeToInteger(), Mask);
return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2)); return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));
} }

10
llvm/test/CodeGen/AArch64/cond-sel.ll
View File

@ -214,3 +214,13 @@ define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
ret void ret void
; CHECK: ret ; CHECK: ret
} }
define <1 x i1> @test_wide_comparison(i32 %in) {
; CHECK-LABEL: test_wide_comparison:
; CHECK: cmp w0, #1234
; CHECK: cset
%tmp = icmp sgt i32 %in, 1234
%res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer
ret <1 x i1> %res
}