From c20b46da2f48a76f2c2affb290d8073e9ce2aab4 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 1 Oct 2017 23:53:53 +0000 Subject: [PATCH] [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register®ister form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register®ister form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register®ister form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639 --- .../X86/MCTargetDesc/X86MCCodeEmitter.cpp | 2 +- llvm/lib/Target/X86/X86InstrArithmetic.td | 21 +++++++++---------- llvm/lib/Target/X86/X86InstrInfo.cpp | 8 +++---- llvm/lib/Target/X86/X86InstrInfo.td | 16 +++++++------- llvm/lib/Target/X86/X86MacroFusion.cpp | 8 +++---- llvm/lib/Target/X86/X86SchedHaswell.td | 4 ++-- llvm/lib/Target/X86/X86SchedSandyBridge.td | 4 ++-- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 4 ++-- llvm/test/CodeGen/X86/absolute-bit-mask.ll | 2 +- .../CodeGen/X86/post-ra-sched-with-debug.mir | 2 +- llvm/test/CodeGen/X86/testl-commute.ll | 6 +++--- llvm/test/MC/Disassembler/X86/x86-16.txt | 4 ++-- llvm/test/MC/X86/intel-syntax.s | 16 +++++++------- llvm/test/MC/X86/x86-16.s | 4 ++-- llvm/test/MC/X86/x86-32.s | 4 ++-- 15 files changed, 52 insertions(+), 53 deletions(-) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp index 10e2bbc64d3c..d12d2b689b3d 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -380,7 +380,7 @@ void X86MCCodeEmitter::emitMemModRMByte(const MCInst &MI, unsigned Op, return X86::reloc_riprel_4byte_movq_load; case X86::CALL64m: case X86::JMP64m: - case X86::TEST64rm: + case X86::TEST64mr: case X86::ADC64rm: case X86::ADD64rm: case X86::AND64rm: diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index 26771e0dfcd8..95f9e84af819 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -652,9 +652,8 @@ class ITy opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, // BinOpRR - Instructions like "add reg, reg, reg". class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, - dag outlist, list pattern, InstrItinClass itin, - Format f = MRMDestReg> - : ITy pattern, InstrItinClass itin> + : ITy, Sched<[WriteALU]>; @@ -662,11 +661,11 @@ class BinOpRR opcode, string mnemonic, X86TypeInfo typeinfo, // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has // just a EFLAGS as a result. class BinOpRR_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDPatternOperator opnode, Format f = MRMDestReg> + SDPatternOperator opnode> : BinOpRR; + IIC_BIN_NONMEM>; // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has // both a regclass and EFLAGS as a result. @@ -727,7 +726,7 @@ class BinOpRM opcode, string mnemonic, X86TypeInfo typeinfo, // BinOpRM_F - Instructions like "cmp reg, [mem]". class BinOpRM_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDPatternOperator opnode> + SDNode opnode> : BinOpRM; @@ -837,7 +836,7 @@ class BinOpMR_RMW_FF opcode, string mnemonic, X86TypeInfo typeinfo, // BinOpMR_F - Instructions like "cmp [mem], reg". class BinOpMR_F opcode, string mnemonic, X86TypeInfo typeinfo, - SDNode opnode> + SDPatternOperator opnode> : BinOpMR; @@ -1224,10 +1223,10 @@ let isCompare = 1 in { def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat>; } // isCommutable - def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>; - def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>; - def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>; - def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>; + def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , X86testpat>; + def TEST16mr : BinOpMR_F<0x84, "test", Xi16, X86testpat>; + def TEST32mr : BinOpMR_F<0x84, "test", Xi32, X86testpat>; + def TEST64mr : BinOpMR_F<0x84, "test", Xi64, X86testpat>; def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 6dcfa97b8515..d7a33f8507e4 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -375,9 +375,13 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD }, { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD }, { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD }, + { X86::TEST16rr, X86::TEST16mr, TB_FOLDED_LOAD }, { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD }, + { X86::TEST32rr, X86::TEST32mr, TB_FOLDED_LOAD }, { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD }, + { X86::TEST64rr, X86::TEST64mr, TB_FOLDED_LOAD }, { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD }, + { X86::TEST8rr, X86::TEST8mr, TB_FOLDED_LOAD }, // AVX 128-bit versions of foldable instructions { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE }, @@ -608,10 +612,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI) { X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE }, { X86::SQRTSSr, X86::SQRTSSm, 0 }, { X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE }, - { X86::TEST16rr, X86::TEST16rm, 0 }, - { X86::TEST32rr, X86::TEST32rm, 0 }, - { X86::TEST64rr, X86::TEST64rm, 0 }, - { X86::TEST8rr, X86::TEST8rm, 0 }, // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, { X86::UCOMISSrr, X86::UCOMISSrm, 0 }, diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 594b07ad320d..b76baac4bdfb 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -3236,14 +3236,14 @@ defm : ShiftRotateByOneAlias<"ror", "ROR">; FIXME */ // test: We accept "testX , " and "testX , " as synonyms. -def : InstAlias<"test{b}\t{$val, $mem|$mem, $val}", - (TEST8rm GR8 :$val, i8mem :$mem), 0>; -def : InstAlias<"test{w}\t{$val, $mem|$mem, $val}", - (TEST16rm GR16:$val, i16mem:$mem), 0>; -def : InstAlias<"test{l}\t{$val, $mem|$mem, $val}", - (TEST32rm GR32:$val, i32mem:$mem), 0>; -def : InstAlias<"test{q}\t{$val, $mem|$mem, $val}", - (TEST64rm GR64:$val, i64mem:$mem), 0>; +def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", + (TEST8mr i8mem :$mem, GR8 :$val), 0>; +def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", + (TEST16mr i16mem:$mem, GR16:$val), 0>; +def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", + (TEST32mr i32mem:$mem, GR32:$val), 0>; +def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", + (TEST64mr i64mem:$mem, GR64:$val), 0>; // xchg: We accept "xchgX , " and "xchgX , " as synonyms. def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", diff --git a/llvm/lib/Target/X86/X86MacroFusion.cpp b/llvm/lib/Target/X86/X86MacroFusion.cpp index d3ef7aa8d6c6..0dd13077c37e 100644 --- a/llvm/lib/Target/X86/X86MacroFusion.cpp +++ b/llvm/lib/Target/X86/X86MacroFusion.cpp @@ -82,10 +82,10 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII, case X86::TEST32i32: case X86::TEST64i32: case X86::TEST64ri32: - case X86::TEST8rm: - case X86::TEST16rm: - case X86::TEST32rm: - case X86::TEST64rm: + case X86::TEST8mr: + case X86::TEST16mr: + case X86::TEST32mr: + case X86::TEST64mr: case X86::TEST8ri_NOREX: case X86::AND16i16: case X86::AND16ri: diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 3523601a4bd6..c2b188b8846a 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -2099,9 +2099,9 @@ def: InstRW<[HWWriteResGroup18], (instregex "OR8rm")>; def: InstRW<[HWWriteResGroup18], (instregex "POP(16|32|64)r(mr?)")>; def: InstRW<[HWWriteResGroup18], (instregex "SUB(16|32|64)rm")>; def: InstRW<[HWWriteResGroup18], (instregex "SUB8rm")>; -def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[HWWriteResGroup18], (instregex "TEST(16|32|64)mr")>; def: InstRW<[HWWriteResGroup18], (instregex "TEST8mi")>; -def: InstRW<[HWWriteResGroup18], (instregex "TEST8rm")>; +def: InstRW<[HWWriteResGroup18], (instregex "TEST8mr")>; def: InstRW<[HWWriteResGroup18], (instregex "XOR(16|32|64)rm")>; def: InstRW<[HWWriteResGroup18], (instregex "XOR8rm")>; diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 2717a409ef6b..593e9b33aacd 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -2010,9 +2010,9 @@ def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mi8")>; def: InstRW<[SBWriteResGroup70], (instregex "SUB(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "SUB8mi")>; def: InstRW<[SBWriteResGroup70], (instregex "SUB8mr")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[SBWriteResGroup70], (instregex "TEST(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "TEST8mi")>; -def: InstRW<[SBWriteResGroup70], (instregex "TEST8rm")>; +def: InstRW<[SBWriteResGroup70], (instregex "TEST8mr")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mi8")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR(16|32|64)mr")>; def: InstRW<[SBWriteResGroup70], (instregex "XOR8mi")>; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 2aaa56e02dd9..d542ddcc6ebc 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -1634,9 +1634,9 @@ def: InstRW<[SKLWriteResGroup21], (instregex "OR8rm")>; def: InstRW<[SKLWriteResGroup21], (instregex "POP(16|32|64)r(mr?)")>; def: InstRW<[SKLWriteResGroup21], (instregex "SUB(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup21], (instregex "SUB8rm")>; -def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)rm")>; +def: InstRW<[SKLWriteResGroup21], (instregex "TEST(16|32|64)mr")>; def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mi")>; -def: InstRW<[SKLWriteResGroup21], (instregex "TEST8rm")>; +def: InstRW<[SKLWriteResGroup21], (instregex "TEST8mr")>; def: InstRW<[SKLWriteResGroup21], (instregex "XOR(16|32|64)rm")>; def: InstRW<[SKLWriteResGroup21], (instregex "XOR8rm")>; diff --git a/llvm/test/CodeGen/X86/absolute-bit-mask.ll b/llvm/test/CodeGen/X86/absolute-bit-mask.ll index 6e119494ac38..818952dc4538 100644 --- a/llvm/test/CodeGen/X86/absolute-bit-mask.ll +++ b/llvm/test/CodeGen/X86/absolute-bit-mask.ll @@ -43,7 +43,7 @@ f: define void @foo64(i64* %ptr) { %load = load i64, i64* %ptr ; CHECK: movabsq $bit_mask64, %rax - ; CHECK: testq (%rdi), %rax + ; CHECK: testq %rax, (%rdi) %and = and i64 %load, ptrtoint (i8* @bit_mask64 to i64) %icmp = icmp eq i64 %and, 0 br i1 %icmp, label %t, label %f diff --git a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir index efc384d36d09..ee07571d17bf 100644 --- a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir +++ b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir @@ -292,7 +292,7 @@ body: | %rcx = CMOVNE64rr killed %rcx, killed %rdx, implicit killed %eflags %rcx = OR64rr killed %rcx, killed %rsi, implicit-def dead %eflags %rdx = MOVSX64rm32 %rbx, 1, _, 0, _ :: (load 4, align 8) - TEST32rm killed %eax, killed %rcx, 4, killed %rdx, 0, _, implicit-def %eflags :: (load 4) + TEST32mr killed %rcx, 4, killed %rdx, 0, _, killed %eax, implicit-def %eflags :: (load 4) JNE_1 %bb.2, implicit %eflags JMP_1 %bb.3 diff --git a/llvm/test/CodeGen/X86/testl-commute.ll b/llvm/test/CodeGen/X86/testl-commute.ll index a9a9e581d995..43e095aecd06 100644 --- a/llvm/test/CodeGen/X86/testl-commute.ll +++ b/llvm/test/CodeGen/X86/testl-commute.ll @@ -9,7 +9,7 @@ target triple = "x86_64-apple-darwin7" define i32 @test(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -30,7 +30,7 @@ bb1: ; preds = %entry define i32 @test2(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test2: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: @@ -51,7 +51,7 @@ bb1: ; preds = %entry define i32 @test3(i32* %P, i32* %G) nounwind { ; CHECK-LABEL: test3: ; CHECK-NOT: ret -; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: testl %{{.*}}, (%{{.*}}) ; CHECK: ret entry: diff --git a/llvm/test/MC/Disassembler/X86/x86-16.txt b/llvm/test/MC/Disassembler/X86/x86-16.txt index 407b695ef636..4099ea68247a 100644 --- a/llvm/test/MC/Disassembler/X86/x86-16.txt +++ b/llvm/test/MC/Disassembler/X86/x86-16.txt @@ -318,10 +318,10 @@ # CHECK: sysretl 0x0f 0x07 -# CHECK: testl -24(%ebp), %ecx +# CHECK: testl %ecx, -24(%ebp) 0x67 0x66 0x85 0x4d 0xe8 -# CHECK: testl -24(%ebp), %ecx +# CHECK: testl %ecx, -24(%ebp) 0x67 0x66 0x85 0x4d 0xe8 # CHECK: pushw %cs diff --git a/llvm/test/MC/X86/intel-syntax.s b/llvm/test/MC/X86/intel-syntax.s index 21bec91d83a2..5e118674f92f 100644 --- a/llvm/test/MC/X86/intel-syntax.s +++ b/llvm/test/MC/X86/intel-syntax.s @@ -532,14 +532,14 @@ xchg [ECX], EAX xchg AX, [ECX] xchg [ECX], AX -// CHECK: testq (%ecx), %rax -// CHECK: testq (%ecx), %rax -// CHECK: testl (%ecx), %eax -// CHECK: testl (%ecx), %eax -// CHECK: testw (%ecx), %ax -// CHECK: testw (%ecx), %ax -// CHECK: testb (%ecx), %al -// CHECK: testb (%ecx), %al +// CHECK: testq %rax, (%ecx) +// CHECK: testq %rax, (%ecx) +// CHECK: testl %eax, (%ecx) +// CHECK: testl %eax, (%ecx) +// CHECK: testw %ax, (%ecx) +// CHECK: testw %ax, (%ecx) +// CHECK: testb %al, (%ecx) +// CHECK: testb %al, (%ecx) test RAX, [ECX] test [ECX], RAX test EAX, [ECX] diff --git a/llvm/test/MC/X86/x86-16.s b/llvm/test/MC/X86/x86-16.s index b95f66ef84d8..5ab1f23d7f23 100644 --- a/llvm/test/MC/X86/x86-16.s +++ b/llvm/test/MC/X86/x86-16.s @@ -406,9 +406,9 @@ sysretl // CHECK: encoding: [0x0f,0x07] testl %ecx, -24(%ebp) -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) testl -24(%ebp), %ecx -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) push %cs diff --git a/llvm/test/MC/X86/x86-32.s b/llvm/test/MC/X86/x86-32.s index f3633dcffef4..6cba31adbb48 100644 --- a/llvm/test/MC/X86/x86-32.s +++ b/llvm/test/MC/X86/x86-32.s @@ -528,9 +528,9 @@ sysretl // rdar://8018260 testl %ecx, -24(%ebp) -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) testl -24(%ebp), %ecx -// CHECK: testl -24(%ebp), %ecx +// CHECK: testl %ecx, -24(%ebp) // rdar://8407242