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[Power9] Add new instructions for floating point status and control registers. 

Added the following P9 instructions: mffsce, mffscdrn, mffscdrni, mffscrn,
  mffscrni, mffsl

Differential Revision: https://reviews.llvm.org/D37167

llvm-svn: 311903
This commit is contained in:
Stefan Pintilie 2017-08-28 18:46:01 +00:00
parent 3763f0e00d
commit c35e4de388
4 changed files with 127 additions and 0 deletions
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62
llvm/lib/Target/PowerPC/PPCInstrFormats.td
View File

@ -725,6 +725,68 @@ class XForm_43<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = RC;
}
class X_FRT5_XO2_XO3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2, bits<10> xo,
dag OOL, dag IOL, string asmstr, InstrItinClass itin,
list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let Pattern = pattern;
let Inst{6-10} = RST;
let Inst{11-12} = xo1;
let Inst{13-15} = xo2;
let Inst{16-20} = 0;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class X_FRT5_XO2_XO3_FRB5_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let Pattern = pattern;
bits<5> FRB;
let Inst{6-10} = RST;
let Inst{11-12} = xo1;
let Inst{13-15} = xo2;
let Inst{16-20} = FRB;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class X_FRT5_XO2_XO3_DRM3_XO10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let Pattern = pattern;
bits<3> DRM;
let Inst{6-10} = RST;
let Inst{11-12} = xo1;
let Inst{13-15} = xo2;
let Inst{16-17} = 0;
let Inst{18-20} = DRM;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class X_FRT5_XO2_XO3_RM2_X10<bits<6> opcode, bits<2> xo1, bits<3> xo2,
bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let Pattern = pattern;
bits<2> RM;
let Inst{6-10} = RST;
let Inst{11-12} = xo1;
let Inst{13-15} = xo2;
let Inst{16-18} = 0;
let Inst{19-20} = RM;
let Inst{21-30} = xo;
let Inst{31} = 0;
}
class XForm_0<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {

29
llvm/lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -2571,6 +2571,35 @@ let Uses = [RM] in {
let Defs = [CR1] in
def MFFSo : XForm_42<63, 583, (outs f8rc:$rT), (ins),
"mffs. $rT", IIC_IntMFFS, []>, isDOT;
def MFFSCE : X_FRT5_XO2_XO3_XO10<63, 0, 1, 583, (outs f8rc:$rT), (ins),
"mffsce $rT", IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCDRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 4, 583, (outs f8rc:$rT),
(ins f8rc:$FRB), "mffscdrn $rT, $FRB",
IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCDRNI : X_FRT5_XO2_XO3_DRM3_XO10<63, 2, 5, 583, (outs f8rc:$rT),
(ins u3imm:$DRM),
"mffscdrni $rT, $DRM",
IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCRN : X_FRT5_XO2_XO3_FRB5_XO10<63, 2, 6, 583, (outs f8rc:$rT),
(ins f8rc:$FRB), "mffscrn $rT, $FRB",
IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSCRNI : X_FRT5_XO2_XO3_RM2_X10<63, 2, 7, 583, (outs f8rc:$rT),
(ins u2imm:$RM), "mffscrni $rT, $RM",
IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
def MFFSL : X_FRT5_XO2_XO3_XO10<63, 3, 0, 583, (outs f8rc:$rT), (ins),
"mffsl $rT", IIC_IntMFFS, []>,
PPC970_DGroup_Single, PPC970_Unit_FPU;
}
let Predicates = [IsISA3_0] in {

18
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-fp.txt
View File

@ -342,6 +342,24 @@
# CHECK: mffs. 7
0xfc 0xe0 0x04 0x8f
# CHECK: mffsce 2
0xfc 0x41 0x04 0x8e
# CHECK: mffscdrn 2, 3
0xfc 0x54 0x1c 0x8e
# CHECK: mffscdrni 2, 3
0xfc 0x55 0x1c 0x8e
# CHECK: mffscrn 2, 3
0xfc 0x56 0x1c 0x8e
# CHECK: mffscrni 2, 3
0xfc 0x57 0x1c 0x8e
# CHECK: mffsl 2
0xfc 0x58 0x04 0x8e
# CHECK: mcrfs 4, 5
0xfe 0x14 0x00 0x80

18
llvm/test/MC/PowerPC/ppc64-encoding-fp.s
View File

@ -382,6 +382,24 @@
# CHECK-BE: mffs. 7 # encoding: [0xfc,0xe0,0x04,0x8f]
# CHECK-LE: mffs. 7 # encoding: [0x8f,0x04,0xe0,0xfc]
mffs. 7
# CHECK-BE: mffsce 2 # encoding: [0xfc,0x41,0x04,0x8e]
# CHECK-LE: mffsce 2 # encoding: [0x8e,0x04,0x41,0xfc]
mffsce 2
# CHECK-BE: mffscdrn 2, 3 # encoding: [0xfc,0x54,0x1c,0x8e]
# CHECK-LE: mffscdrn 2, 3 # encoding: [0x8e,0x1c,0x54,0xfc]
mffscdrn 2, 3
# CHECK-BE: mffscdrni 2, 3 # encoding: [0xfc,0x55,0x1c,0x8e]
# CHECK-LE: mffscdrni 2, 3 # encoding: [0x8e,0x1c,0x55,0xfc]
mffscdrni 2, 3
# CHECK-BE: mffscrn 2, 3 # encoding: [0xfc,0x56,0x1c,0x8e]
# CHECK-LE: mffscrn 2, 3 # encoding: [0x8e,0x1c,0x56,0xfc]
mffscrn 2, 3
# CHECK-BE: mffscrni 2, 3 # encoding: [0xfc,0x57,0x1c,0x8e]
# CHECK-LE: mffscrni 2, 3 # encoding: [0x8e,0x1c,0x57,0xfc]
mffscrni 2, 3
# CHECK-BE: mffsl 2 # encoding: [0xfc,0x58,0x04,0x8e]
# CHECK-LE: mffsl 2 # encoding: [0x8e,0x04,0x58,0xfc]
mffsl 2
# CHECK-BE: mcrfs 4, 5 # encoding: [0xfe,0x14,0x00,0x80]
# CHECK-LE: mcrfs 4, 5 # encoding: [0x80,0x00,0x14,0xfe]
mcrfs 4, 5