forked from OSchip/llvm-project
[InstCombine] add test for assume in block with unreachable (PR47416); NFC
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Sanjay Patel
parent
b3e139444f
commit
c5d6b2b7e5
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@ -1,66 +1,56 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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define i32 @foo1(i32* %a) #0 {
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; CHECK-LABEL: @foo1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A:%.*]], align 32
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; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i32* [[A]] to i64
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; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31
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; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
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; CHECK-NEXT: ret i32 [[TMP0]]
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;
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entry:
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%0 = load i32, i32* %a, align 4
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declare void @llvm.assume(i1) #1
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; Check that the alignment has been upgraded and that the assume has not
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; been removed:
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define i32 @foo1(i32* %a) #0 {
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; CHECK-LABEL: @foo1(
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; CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[A:%.*]], align 32
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; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i32* [[A]] to i64
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; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31
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; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
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; CHECK-NEXT: ret i32 [[T0]]
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;
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%t0 = load i32, i32* %a, align 4
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%ptrint = ptrtoint i32* %a to i64
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%maskedptr = and i64 %ptrint, 31
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%maskcond = icmp eq i64 %maskedptr, 0
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tail call void @llvm.assume(i1 %maskcond)
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ret i32 %0
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ret i32 %t0
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}
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; Same check as in @foo1, but make sure it works if the assume is first too.
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define i32 @foo2(i32* %a) #0 {
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; CHECK-LABEL: @foo2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PTRINT:%.*]] = ptrtoint i32* [[A:%.*]] to i64
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; CHECK-NEXT: [[MASKEDPTR:%.*]] = and i64 [[PTRINT]], 31
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; CHECK-NEXT: [[MASKCOND:%.*]] = icmp eq i64 [[MASKEDPTR]], 0
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[MASKCOND]])
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 32
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; CHECK-NEXT: ret i32 [[TMP0]]
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; CHECK-NEXT: [[T0:%.*]] = load i32, i32* [[A]], align 32
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; CHECK-NEXT: ret i32 [[T0]]
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;
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entry:
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; Same check as in @foo1, but make sure it works if the assume is first too.
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%ptrint = ptrtoint i32* %a to i64
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%maskedptr = and i64 %ptrint, 31
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%maskcond = icmp eq i64 %maskedptr, 0
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tail call void @llvm.assume(i1 %maskcond)
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%0 = load i32, i32* %a, align 4
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ret i32 %0
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%t0 = load i32, i32* %a, align 4
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ret i32 %t0
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}
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declare void @llvm.assume(i1) #1
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define i32 @simple(i32 %a) #1 {
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; CHECK-LABEL: @simple(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[A:%.*]], 4
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
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; CHECK-NEXT: ret i32 4
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;
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entry:
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%cmp = icmp eq i32 %a, 4
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tail call void @llvm.assume(i1 %cmp)
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ret i32 %a
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@ -68,72 +58,55 @@ entry:
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define i32 @can1(i1 %a, i1 %b, i1 %c) {
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; CHECK-LABEL: @can1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: call void @llvm.assume(i1 [[A:%.*]])
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; CHECK-NEXT: call void @llvm.assume(i1 [[B:%.*]])
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; CHECK-NEXT: call void @llvm.assume(i1 [[C:%.*]])
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; CHECK-NEXT: ret i32 5
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;
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entry:
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%and1 = and i1 %a, %b
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%and = and i1 %and1, %c
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tail call void @llvm.assume(i1 %and)
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ret i32 5
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}
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define i32 @can2(i1 %a, i1 %b, i1 %c) {
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; CHECK-LABEL: @can2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[TMP0:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP0]])
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; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[B:%.*]], true
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; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[A:%.*]], true
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP1]])
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; CHECK-NEXT: [[TMP2:%.*]] = xor i1 [[B:%.*]], true
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; CHECK-NEXT: call void @llvm.assume(i1 [[TMP2]])
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; CHECK-NEXT: ret i32 5
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;
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entry:
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%v = or i1 %a, %b
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%w = xor i1 %v, 1
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tail call void @llvm.assume(i1 %w)
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ret i32 5
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}
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define i32 @bar1(i32 %a) #0 {
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; CHECK-LABEL: @bar1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
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; CHECK-NEXT: ret i32 1
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;
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entry:
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%and1 = and i32 %a, 3
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%and = and i32 %a, 7
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%cmp = icmp eq i32 %and, 1
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tail call void @llvm.assume(i1 %cmp)
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ret i32 %and1
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}
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define i32 @bar2(i32 %a) #0 {
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; CHECK-LABEL: @bar2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[AND:%.*]] = and i32 [[A:%.*]], 7
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 1
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP]])
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; CHECK-NEXT: ret i32 1
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;
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entry:
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%and = and i32 %a, 7
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%cmp = icmp eq i32 %and, 1
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tail call void @llvm.assume(i1 %cmp)
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%and1 = and i32 %a, 3
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ret i32 %and1
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}
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@ -176,15 +149,11 @@ define i32 @bar4(i32 %a, i32 %b) {
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;
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entry:
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%and1 = and i32 %b, 3
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%and = and i32 %a, 7
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%cmp = icmp eq i32 %and, 1
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tail call void @llvm.assume(i1 %cmp)
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%cmp2 = icmp eq i32 %a, %b
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tail call void @llvm.assume(i1 %cmp2)
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ret i32 %and1
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}
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@ -377,10 +346,10 @@ define i32 @assumption_conflicts_with_known_bits(i32 %a, i32 %b) {
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define void @debug_interference(i8 %x) {
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; CHECK-LABEL: @debug_interference(
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ne i8 [[X:%.*]], 0
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, metadata !7, metadata !DIExpression()), !dbg !9
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, [[META7:metadata !.*]], metadata !DIExpression()), [[DBG9:!dbg !.*]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 false)
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, metadata !7, metadata !DIExpression()), !dbg !9
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, metadata !7, metadata !DIExpression()), !dbg !9
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, [[META7]], metadata !DIExpression()), [[DBG9]]
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; CHECK-NEXT: tail call void @llvm.dbg.value(metadata i32 5, [[META7]], metadata !DIExpression()), [[DBG9]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP2]])
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; CHECK-NEXT: ret void
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;
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@ -532,7 +501,6 @@ define void @always_true_assumption() {
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;
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call void @llvm.assume(i1 true)
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ret void
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}
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; The alloca guarantees that the low bits of %a are zero because of alignment.
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@ -588,6 +556,47 @@ define void @PR36270(i32 %b) {
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unreachable
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}
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; PR47416
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define i32 @unreachable_assume(i32 %x, i32 %y) {
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; CHECK-LABEL: @unreachable_assume(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp sgt i32 [[X:%.*]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq i32 [[Y:%.*]], 1
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP0]], [[CMP1]]
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[OR]])
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; CHECK-NEXT: [[CMP2:%.*]] = icmp eq i32 [[X]], 1
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; CHECK-NEXT: br i1 [[CMP2]], label [[IF:%.*]], label [[EXIT:%.*]]
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; CHECK: if:
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; CHECK-NEXT: [[A:%.*]] = and i32 [[Y]], -2
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; CHECK-NEXT: [[CMP3:%.*]] = icmp ne i32 [[A]], 104
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP3]])
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i32 [[X]], 2
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[CMP4]])
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; CHECK-NEXT: unreachable
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;
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entry:
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%cmp0 = icmp sgt i32 %x, 1
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%cmp1 = icmp eq i32 %y, 1
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%or = or i1 %cmp0, %cmp1
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tail call void @llvm.assume(i1 %or)
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%cmp2 = icmp eq i32 %x, 1
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br i1 %cmp2, label %if, label %exit
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if:
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%a = and i32 %y, -2
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%cmp3 = icmp ne i32 %a, 104
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tail call void @llvm.assume(i1 %cmp3)
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br label %exit
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exit:
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%cmp4 = icmp eq i32 %x, 2
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tail call void @llvm.assume(i1 %cmp4)
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unreachable
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}
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declare void @llvm.dbg.value(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!0}
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