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The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp 

llvm-svn: 184292
This commit is contained in:
Vladimir Medic 2013-06-19 10:14:36 +00:00
parent db1bf3fd2d
commit c69605951f
2 changed files with 10 additions and 19 deletions
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15
llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@ -357,36 +357,23 @@ public:
bool isCPURegsAsm() const { bool isCPURegsAsm() const {
return Kind == k_Register && Reg.Kind == Kind_CPURegs; return Kind == k_Register && Reg.Kind == Kind_CPURegs;
} }
void addCPURegsAsmOperands(MCInst &Inst, unsigned N) const { void addRegAsmOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Reg.RegNum)); Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
} }
bool isCPU64RegsAsm() const { bool isCPU64RegsAsm() const {
return Kind == k_Register && Reg.Kind == Kind_CPU64Regs; return Kind == k_Register && Reg.Kind == Kind_CPU64Regs;
} }
void addCPU64RegsAsmOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
}
bool isHWRegsAsm() const { bool isHWRegsAsm() const {
assert((Kind == k_Register) && "Invalid access!"); assert((Kind == k_Register) && "Invalid access!");
return Reg.Kind == Kind_HWRegs; return Reg.Kind == Kind_HWRegs;
} }
void addHWRegsAsmOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
}
bool isHW64RegsAsm() const { bool isHW64RegsAsm() const {
assert((Kind == k_Register) && "Invalid access!"); assert((Kind == k_Register) && "Invalid access!");
return Reg.Kind == Kind_HW64Regs; return Reg.Kind == Kind_HW64Regs;
} }
void addHW64RegsAsmOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
}
void addCCRAsmOperands(MCInst &Inst, unsigned N) const {
Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
}
bool isCCRAsm() const { bool isCCRAsm() const {
assert((Kind == k_Register) && "Invalid access!"); assert((Kind == k_Register) && "Invalid access!");

14
llvm/lib/Target/Mips/MipsRegisterInfo.td
View File

@ -388,17 +388,21 @@ def ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
// Register Operands. // Register Operands.
def CPURegsAsmOperand : AsmOperandClass {
class MipsAsmRegOperand : AsmOperandClass {
let RenderMethod = "addRegAsmOperands";
}
def CPURegsAsmOperand : MipsAsmRegOperand {
let Name = "CPURegsAsm"; let Name = "CPURegsAsm";
let ParserMethod = "parseCPURegs"; let ParserMethod = "parseCPURegs";
} }
def CPU64RegsAsmOperand : AsmOperandClass { def CPU64RegsAsmOperand : MipsAsmRegOperand {
let Name = "CPU64RegsAsm"; let Name = "CPU64RegsAsm";
let ParserMethod = "parseCPU64Regs"; let ParserMethod = "parseCPU64Regs";
} }
def CCRAsmOperand : AsmOperandClass { def CCRAsmOperand : MipsAsmRegOperand {
let Name = "CCRAsm"; let Name = "CCRAsm";
let ParserMethod = "parseCCRRegs"; let ParserMethod = "parseCCRRegs";
} }
@ -415,12 +419,12 @@ def CCROpnd : RegisterOperand<CCR, "printCPURegs"> {
let ParserMatchClass = CCRAsmOperand; let ParserMatchClass = CCRAsmOperand;
} }
def HWRegsAsmOperand : AsmOperandClass { def HWRegsAsmOperand : MipsAsmRegOperand {
let Name = "HWRegsAsm"; let Name = "HWRegsAsm";
let ParserMethod = "parseHWRegs"; let ParserMethod = "parseHWRegs";
} }
def HW64RegsAsmOperand : AsmOperandClass { def HW64RegsAsmOperand : MipsAsmRegOperand {
let Name = "HW64RegsAsm"; let Name = "HW64RegsAsm";
let ParserMethod = "parseHW64Regs"; let ParserMethod = "parseHW64Regs";
} }