wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Propagate zest through logical shift. 

llvm-svn: 91378
This commit is contained in:
Evan Cheng 2009-12-15 00:41:36 +00:00
parent d5218331f7
commit ca7c690d3b
3 changed files with 61 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3278,6 +3278,16 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
if (SCC.getNode()) return SCC;
}
// (zext (shl (zext x), y)) -> (shl (zext x), (zext y))
if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
N0.hasOneUse()) {
DebugLoc dl = N->getDebugLoc();
return DAG.getNode(N0.getOpcode(), dl, VT,
DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)),
DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(1)));
}
return SDValue();
}

13
llvm/test/CodeGen/X86/setcc.ll Normal file
View File

@ -0,0 +1,13 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
entry:
; CHECK: t1:
; CHECK: seta %al
; CHECK: movzbl %al, %eax
; CHECK: shll $5, %eax
%0 = icmp ugt i16 %x, 26 ; <i1> [#uses=1]
%iftmp.1.0 = select i1 %0, i16 32, i16 0 ; <i16> [#uses=1]
ret i16 %iftmp.1.0
}

38
llvm/test/CodeGen/X86/zext-shl.ll Normal file
View File

@ -0,0 +1,38 @@
; RUN: llc < %s -march=x86 | FileCheck %s
define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
entry:
; CHECK: t1:
; CHECK: shll
; CHECK-NOT: movzwl
; CHECK: ret
%0 = zext i8 %x to i16
%1 = shl i16 %0, 5
%2 = zext i16 %1 to i32
ret i32 %2
}
define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
entry:
; CHECK: t2:
; CHECK: shrl
; CHECK-NOT: movzwl
; CHECK: ret
%0 = zext i8 %x to i16
%1 = lshr i16 %0, 3
%2 = zext i16 %1 to i32
ret i32 %2
}
define i32 @t3(i8 zeroext %x, i8 zeroext %y) nounwind readnone ssp {
entry:
; CHECK: t3:
; CHECK: shll
; CHECK-NOT: movzwl
; CHECK: ret
%0 = zext i8 %x to i16
%1 = zext i8 %y to i16
%2 = shl i16 %0, %1
%3 = zext i16 %2 to i32
ret i32 %3
}