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[ARM] NEON 32-bit scalar moves are also available in VFPv2 

The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.

Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.

llvm-svn: 220288
This commit is contained in:
Oliver Stannard 2014-10-21 11:49:14 +00:00
parent c0126864a0
commit cdb8db8d3c
2 changed files with 35 additions and 2 deletions
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5
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -5437,7 +5437,7 @@ def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
IIC_VMOVSI, "vmov", "32", "$R, $V$lane", IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
[(set GPR:$R, (extractelt (v2i32 DPR:$V), [(set GPR:$R, (extractelt (v2i32 DPR:$V),
imm:$lane))]>, imm:$lane))]>,
Requires<[HasNEON, HasFastVGETLNi32]> { Requires<[HasVFP2, HasFastVGETLNi32]> {
let Inst{21} = lane{0}; let Inst{21} = lane{0};
} }
// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
@ -5505,7 +5505,8 @@ def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
(ins DPR:$src1, GPR:$R, VectorIndex32:$lane), (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
IIC_VMOVISL, "vmov", "32", "$V$lane, $R", IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
[(set DPR:$V, (insertelt (v2i32 DPR:$src1), [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
GPR:$R, imm:$lane))]> { GPR:$R, imm:$lane))]>,
Requires<[HasVFP2]> {
let Inst{21} = lane{0}; let Inst{21} = lane{0};
// This instruction is equivalent as // This instruction is equivalent as
// $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm) // $V = INSERT_SUBREG $src1, $R, translateImmToSubIdx($imm)

32
llvm/test/MC/ARM/neon-mov-vfp.s Normal file
View File

@ -0,0 +1,32 @@
@ RUN: not llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
@ RUN: not llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK
@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon < %s 2>&1 | FileCheck %s --check-prefix=NEON --check-prefix=CHECK
@ The 32-bit variants of the NEON scalar move instructions are also available
@ to any core with VFPv2
@ CHECK-DAG: vmov.32 d13[0], r6 @ encoding:
@ CHECK-DAG: vmov.32 d17[1], r9 @ encoding:
vmov.32 d13[0], r6
vmov.32 d17[1], r9
@ VFP-DAG: error: instruction requires: NEON
@ VFP-DAG: error: instruction requires: NEON
@ NEON-DAG: vmov.8 d22[5], r2 @ encoding:
@ NEON-DAG: vmov.16 d3[2], r4 @ encoding:
vmov.8 d22[5], r2
vmov.16 d3[2], r4
@ CHECK-DAG: vmov.32 r6, d13[0] @ encoding:
@ CHECK-DAG: vmov.32 r9, d17[1] @ encoding:
vmov.32 r6, d13[0]
vmov.32 r9, d17[1]
@ VFP-DAG: error: instruction requires: NEON
@ VFP-DAG: error: instruction requires: NEON
@ NEON-DAG: vmov.s8 r2, d22[5] @ encoding:
@ NEON-DAG: vmov.u16 r4, d3[2] @ encoding:
vmov.s8 r2, d22[5]
vmov.u16 r4, d3[2]