forked from OSchip/llvm-project
<rdar://problem/13020634>
Fixed the 32, 16, and 8 bit pseudo regs for x86_64 (real reg of "rax" which subvalues "eax", "ax", etc...) to correctly get updated when stepping. Also fixed it so actual registers can specify what other registers must be invalidated when a register is modified. Previously, only pseudo registers could invalidate other registers. Modified the LLDB qRegisterInfo extension to the GDB remote interface to support specifying the containing registers with the new "container-regs" key whose value is a comma separated list of register numbers. Also added a "invalidate-regs" key whose value is also a comma separated list of register numbers. Removed the hack GDBRemoteDynamicRegisterInfo::Addx86_64ConvenienceRegisters() function and modified "debugserver" to specify the registers correctly using the new "container-regs" and "invalidate-regs" keys. llvm-svn: 173096
This commit is contained in:
Greg Clayton
parent
304f6f0a59
commit
ce1ffcf8a2
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@ -134,13 +134,13 @@ GDBRemoteRegisterContext::PrivateSetRegisterValue (uint32_t reg, StringExtractor
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bool success = bytes_copied == reg_byte_size;
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if (success)
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{
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m_reg_valid[reg] = true;
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SetRegisterIsValid(reg, true);
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}
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else if (bytes_copied > 0)
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{
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// Only set register is valid to false if we copied some bytes, else
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// leave it as it was.
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m_reg_valid[reg] = false;
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SetRegisterIsValid(reg, false);
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}
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return success;
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}
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@ -180,7 +180,7 @@ GDBRemoteRegisterContext::ReadRegisterBytes (const RegisterInfo *reg_info, DataE
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const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
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if (!m_reg_valid[reg])
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if (!GetRegisterIsValid(reg))
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{
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Mutex::Locker locker;
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if (gdb_comm.GetSequenceMutex (locker, "Didn't get sequence mutex for read register."))
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@ -207,40 +207,43 @@ GDBRemoteRegisterContext::ReadRegisterBytes (const RegisterInfo *reg_info, DataE
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SetAllRegisterValid (true);
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}
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}
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else if (!reg_info->value_regs)
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{
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// Get each register individually
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GetPrimordialRegister(reg_info, gdb_comm);
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}
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else
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else if (reg_info->value_regs)
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{
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// Process this composite register request by delegating to the constituent
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// primordial registers.
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// Index of the primordial register.
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uint32_t prim_reg_idx;
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bool success = true;
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for (uint32_t idx = 0;
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(prim_reg_idx = reg_info->value_regs[idx]) != LLDB_INVALID_REGNUM;
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++idx)
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for (uint32_t idx = 0; success; ++idx)
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{
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const uint32_t prim_reg = reg_info->value_regs[idx];
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if (prim_reg == LLDB_INVALID_REGNUM)
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break;
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// We have a valid primordial regsiter as our constituent.
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// Grab the corresponding register info.
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const RegisterInfo *prim_reg_info = GetRegisterInfoAtIndex(prim_reg_idx);
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if (!GetPrimordialRegister(prim_reg_info, gdb_comm))
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{
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const RegisterInfo *prim_reg_info = GetRegisterInfoAtIndex(prim_reg);
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if (prim_reg_info == NULL)
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success = false;
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// Some failure occurred. Let's break out of the for loop.
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break;
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else
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{
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// Read the containing register if it hasn't already been read
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if (!GetRegisterIsValid(prim_reg))
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success = GetPrimordialRegister(prim_reg_info, gdb_comm);
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}
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}
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if (success)
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{
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// If we reach this point, all primordial register requests have succeeded.
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// Validate this composite register.
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m_reg_valid[reg_info->kinds[eRegisterKindLLDB]] = true;
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SetRegisterIsValid (reg_info, true);
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}
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}
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else
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{
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// Get each register individually
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GetPrimordialRegister(reg_info, gdb_comm);
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}
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}
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}
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else
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@ -269,7 +272,7 @@ GDBRemoteRegisterContext::ReadRegisterBytes (const RegisterInfo *reg_info, DataE
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}
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// Make sure we got a valid register value after reading it
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if (!m_reg_valid[reg])
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if (!GetRegisterIsValid(reg))
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return false;
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}
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@ -314,7 +317,7 @@ GDBRemoteRegisterContext::SetPrimordialRegister(const lldb_private::RegisterInfo
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packet.Printf (";thread:%4.4" PRIx64 ";", m_thread.GetID());
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// Invalidate just this register
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m_reg_valid[reg] = false;
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SetRegisterIsValid(reg, false);
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if (gdb_comm.SendPacketAndWaitForResponse(packet.GetString().c_str(),
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packet.GetString().size(),
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response,
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@ -387,6 +390,7 @@ GDBRemoteRegisterContext::WriteRegisterBytes (const lldb_private::RegisterInfo *
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{
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StreamString packet;
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StringExtractorGDBRemote response;
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if (m_read_all_at_once)
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{
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// Set all registers in one packet
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@ -414,52 +418,50 @@ GDBRemoteRegisterContext::WriteRegisterBytes (const lldb_private::RegisterInfo *
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}
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}
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}
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else if (!reg_info->value_regs)
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{
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// Set each register individually
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return SetPrimordialRegister(reg_info, gdb_comm);
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}
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else
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{
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// Process this composite register request by delegating to the constituent
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// primordial registers.
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bool success = true;
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// Invalidate this composite register first.
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m_reg_valid[reg_info->kinds[eRegisterKindLLDB]] = false;
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if (reg_info->value_regs)
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{
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// This register is part of another register. In this case we read the actual
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// register data for any "value_regs", and once all that data is read, we will
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// have enough data in our register context bytes for the value of this register
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// Invalidate this composite register first.
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for (uint32_t idx = 0; success; ++idx)
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{
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const uint32_t reg = reg_info->value_regs[idx];
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if (reg == LLDB_INVALID_REGNUM)
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break;
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// We have a valid primordial regsiter as our constituent.
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// Grab the corresponding register info.
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const RegisterInfo *value_reg_info = GetRegisterInfoAtIndex(reg);
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if (value_reg_info == NULL)
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success = false;
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else
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success = SetPrimordialRegister(value_reg_info, gdb_comm);
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}
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}
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else
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{
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// This is an actual register, write it
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success = SetPrimordialRegister(reg_info, gdb_comm);
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}
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// Index of the primordial register.
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uint32_t prim_reg_idx;
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// For loop index.
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uint32_t idx;
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// Invalidate the invalidate_regs, if present.
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// Check if writing this register will invalidate any other register values?
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// If so, invalidate them
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if (reg_info->invalidate_regs)
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{
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for (idx = 0;
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(prim_reg_idx = reg_info->invalidate_regs[idx]) != LLDB_INVALID_REGNUM;
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++idx)
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for (uint32_t idx = 0, reg = reg_info->invalidate_regs[0];
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reg != LLDB_INVALID_REGNUM;
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reg = reg_info->invalidate_regs[++idx])
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{
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// Grab the invalidate register info.
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const RegisterInfo *prim_reg_info = GetRegisterInfoAtIndex(prim_reg_idx);
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m_reg_valid[prim_reg_info->kinds[eRegisterKindLLDB]] = false;
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}
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}
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bool success = true;
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for (idx = 0;
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(prim_reg_idx = reg_info->value_regs[idx]) != LLDB_INVALID_REGNUM;
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++idx)
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{
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// We have a valid primordial regsiter as our constituent.
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// Grab the corresponding register info.
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const RegisterInfo *prim_reg_info = GetRegisterInfoAtIndex(prim_reg_idx);
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if (!SetPrimordialRegister(prim_reg_info, gdb_comm))
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{
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success = false;
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// Some failure occurred. Let's break out of the for loop.
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break;
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SetRegisterIsValid(reg, false);
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}
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}
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return success;
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}
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}
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@ -633,7 +635,7 @@ GDBRemoteRegisterContext::WriteAllRegisterValues (const lldb::DataBufferSP &data
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const char *restore_src = (const char *)restore_data.PeekData(reg_byte_offset, reg_byte_size);
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if (restore_src)
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{
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if (m_reg_valid[reg])
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if (GetRegisterIsValid(reg))
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{
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const char *current_src = (const char *)m_reg_data.PeekData(reg_byte_offset, reg_byte_size);
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if (current_src)
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@ -652,7 +654,7 @@ GDBRemoteRegisterContext::WriteAllRegisterValues (const lldb::DataBufferSP &data
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if (thread_suffix_supported)
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packet.Printf (";thread:%4.4" PRIx64 ";", m_thread.GetID());
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m_reg_valid[reg] = false;
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SetRegisterIsValid(reg, false);
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if (gdb_comm.SendPacketAndWaitForResponse(packet.GetString().c_str(),
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packet.GetString().size(),
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response,
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@ -931,93 +933,3 @@ GDBRemoteDynamicRegisterInfo::HardcodeARMRegisters(bool from_scratch)
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}
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}
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}
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void
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GDBRemoteDynamicRegisterInfo::Addx86_64ConvenienceRegisters()
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{
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// For eax, ebx, ecx, edx, esi, edi, ebp, esp register mapping.
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static const char* g_mapped_names[] = {
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"rax", "rbx", "rcx", "rdx", "rdi", "rsi", "rbp", "rsp",
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"rax", "rbx", "rcx", "rdx", "rdi", "rsi", "rbp", "rsp",
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"rax", "rbx", "rcx", "rdx",
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"rax", "rbx", "rcx", "rdx", "rdi", "rsi", "rbp", "rsp"
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};
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// These value regs are to be populated with the corresponding primordial register index.
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// For example,
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static uint32_t g_eax_regs[] = { 0, LLDB_INVALID_REGNUM }; // 0 is to be replaced with rax's index.
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static uint32_t g_ebx_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_ecx_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_edx_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_edi_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_esi_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_ebp_regs[] = { 0, LLDB_INVALID_REGNUM };
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static uint32_t g_esp_regs[] = { 0, LLDB_INVALID_REGNUM };
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static RegisterInfo g_conv_register_infos[] =
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{
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// NAME ALT SZ OFF ENCODING FORMAT COMPILER DWARF GENERIC GDB LLDB NATIVE VALUE REGS INVALIDATE REGS
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// ====== ======= == === ============= ============ ===================== ===================== ============================ ==================== ====================== ========== ===============
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{ "eax" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_eax_regs, NULL},
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{ "ebx" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebx_regs, NULL},
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{ "ecx" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ecx_regs, NULL},
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{ "edx" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edx_regs, NULL},
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{ "edi" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edi_regs, NULL},
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{ "esi" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esi_regs, NULL},
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{ "ebp" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebp_regs, NULL},
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{ "esp" , NULL, 4, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esp_regs, NULL},
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{ "ax" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_eax_regs, NULL},
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{ "bx" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebx_regs, NULL},
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{ "cx" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ecx_regs, NULL},
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{ "dx" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edx_regs, NULL},
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{ "di" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edi_regs, NULL},
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{ "si" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esi_regs, NULL},
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{ "bp" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebp_regs, NULL},
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{ "sp" , NULL, 2, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esp_regs, NULL},
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{ "ah" , NULL, 1, 1, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_eax_regs, NULL},
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{ "bh" , NULL, 1, 1, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebx_regs, NULL},
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{ "ch" , NULL, 1, 1, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ecx_regs, NULL},
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{ "dh" , NULL, 1, 1, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edx_regs, NULL},
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{ "al" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_eax_regs, NULL},
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{ "bl" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebx_regs, NULL},
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{ "cl" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ecx_regs, NULL},
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{ "dl" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edx_regs, NULL},
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{ "dil" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_edi_regs, NULL},
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{ "sil" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esi_regs, NULL},
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{ "bpl" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_ebp_regs, NULL},
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{ "spl" , NULL, 1, 0, eEncodingUint , eFormatHex , { LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM , LLDB_INVALID_REGNUM }, g_esp_regs, NULL}
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};
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static const uint32_t num_conv_regs = llvm::array_lengthof(g_mapped_names);
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static ConstString gpr_reg_set ("General Purpose Registers");
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// Add convenience registers to our primordial registers.
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const uint32_t num_primordials = GetNumRegisters();
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uint32_t reg_kind = num_primordials;
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for (uint32_t i=0; i<num_conv_regs; ++i)
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{
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ConstString name;
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ConstString alt_name;
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const char *prim_reg_name = g_mapped_names[i];
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if (prim_reg_name && prim_reg_name[0])
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{
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for (uint32_t j = 0; j < num_primordials; ++j)
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{
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const RegisterInfo *reg_info = GetRegisterInfoAtIndex(j);
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// Find a matching primordial register info entry.
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if (reg_info && reg_info->name && ::strcasecmp(reg_info->name, prim_reg_name) == 0)
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{
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// The name matches the existing primordial entry.
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// Find and assign the offset, and then add this composite register entry.
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g_conv_register_infos[i].byte_offset = reg_info->byte_offset + g_conv_register_infos[i].byte_offset;
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// Update the value_regs and the kinds fields in order to delegate to the primordial register.
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g_conv_register_infos[i].value_regs[0] = j;
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g_conv_register_infos[i].kinds[eRegisterKindLLDB] = ++reg_kind;
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name.SetCString(g_conv_register_infos[i].name);
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AddRegister(g_conv_register_infos[i], name, alt_name, gpr_reg_set);
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}
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}
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}
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}
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}
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@ -57,6 +57,21 @@ public:
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reg_info.name = reg_name.AsCString();
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assert (reg_info.name);
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reg_info.alt_name = reg_alt_name.AsCString(NULL);
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uint32_t i;
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if (reg_info.value_regs)
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{
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for (i=0; reg_info.value_regs[i] != LLDB_INVALID_REGNUM; ++i)
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m_value_regs_map[reg_num].push_back(reg_info.value_regs[i]);
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m_value_regs_map[reg_num].push_back(LLDB_INVALID_REGNUM);
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reg_info.value_regs = m_value_regs_map[reg_num].data();
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}
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if (reg_info.invalidate_regs)
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{
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for (i=0; reg_info.invalidate_regs[i] != LLDB_INVALID_REGNUM; ++i)
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m_invalidate_regs_map[reg_num].push_back(reg_info.invalidate_regs[i]);
|
||||
m_invalidate_regs_map[reg_num].push_back(LLDB_INVALID_REGNUM);
|
||||
reg_info.invalidate_regs = m_invalidate_regs_map[reg_num].data();
|
||||
}
|
||||
m_regs.push_back (reg_info);
|
||||
uint32_t set = GetRegisterSetIndexByName (set_name, true);
|
||||
assert (set < m_sets.size());
|
||||
|
|
@ -156,9 +171,6 @@ public:
|
|||
void
|
||||
HardcodeARMRegisters(bool from_scratch);
|
||||
|
||||
void
|
||||
Addx86_64ConvenienceRegisters();
|
||||
|
||||
protected:
|
||||
//------------------------------------------------------------------
|
||||
// Classes that inherit from GDBRemoteRegisterContext can see and modify these
|
||||
|
|
@ -168,6 +180,7 @@ protected:
|
|||
typedef std::vector <uint32_t> reg_num_collection;
|
||||
typedef std::vector <reg_num_collection> set_reg_num_collection;
|
||||
typedef std::vector <lldb_private::ConstString> name_collection;
|
||||
typedef std::map<uint32_t, reg_num_collection> reg_to_regs_map;
|
||||
|
||||
reg_collection m_regs;
|
||||
set_collection m_sets;
|
||||
|
|
@ -175,6 +188,8 @@ protected:
|
|||
name_collection m_reg_names;
|
||||
name_collection m_reg_alt_names;
|
||||
name_collection m_set_names;
|
||||
reg_to_regs_map m_value_regs_map;
|
||||
reg_to_regs_map m_invalidate_regs_map;
|
||||
size_t m_reg_data_byte_size; // The number of bytes required to store all registers
|
||||
};
|
||||
|
||||
|
|
@ -243,6 +258,34 @@ protected:
|
|||
void
|
||||
SetAllRegisterValid (bool b);
|
||||
|
||||
bool
|
||||
GetRegisterIsValid (uint32_t reg) const
|
||||
{
|
||||
#if defined (LLDB_CONFIGURATION_DEBUG)
|
||||
assert (reg < m_reg_valid.size());
|
||||
#endif
|
||||
if (reg < m_reg_valid.size())
|
||||
return m_reg_valid[reg];
|
||||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
SetRegisterIsValid (const lldb_private::RegisterInfo *reg_info, bool valid)
|
||||
{
|
||||
if (reg_info)
|
||||
return SetRegisterIsValid (reg_info->kinds[lldb::eRegisterKindLLDB], valid);
|
||||
}
|
||||
|
||||
void
|
||||
SetRegisterIsValid (uint32_t reg, bool valid)
|
||||
{
|
||||
#if defined (LLDB_CONFIGURATION_DEBUG)
|
||||
assert (reg < m_reg_valid.size());
|
||||
#endif
|
||||
if (reg < m_reg_valid.size())
|
||||
m_reg_valid[reg] = valid;
|
||||
}
|
||||
|
||||
void
|
||||
SyncThreadState(lldb_private::Process *process); // Assumes the sequence mutex has already been acquired.
|
||||
|
||||
|
|
|
|||
|
|
@ -280,6 +280,8 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
|
|||
ConstString reg_name;
|
||||
ConstString alt_name;
|
||||
ConstString set_name;
|
||||
std::vector<uint32_t> value_regs;
|
||||
std::vector<uint32_t> invalidate_regs;
|
||||
RegisterInfo reg_info = { NULL, // Name
|
||||
NULL, // Alt name
|
||||
0, // byte size
|
||||
|
|
@ -371,11 +373,48 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
|
|||
{
|
||||
reg_info.kinds[eRegisterKindGeneric] = Args::StringToGenericRegister (value.c_str());
|
||||
}
|
||||
else if (name.compare("container-regs") == 0)
|
||||
{
|
||||
std::pair<llvm::StringRef, llvm::StringRef> value_pair;
|
||||
value_pair.second = value;
|
||||
do
|
||||
{
|
||||
value_pair = value_pair.second.split(',');
|
||||
if (!value_pair.first.empty())
|
||||
{
|
||||
value_regs.push_back (Args::StringToUInt32 (value_pair.first.str().c_str()));
|
||||
}
|
||||
} while (!value_pair.second.empty());
|
||||
}
|
||||
else if (name.compare("invalidate-regs") == 0)
|
||||
{
|
||||
std::pair<llvm::StringRef, llvm::StringRef> value_pair;
|
||||
value_pair.second = value;
|
||||
do
|
||||
{
|
||||
value_pair = value_pair.second.split(',');
|
||||
if (!value_pair.first.empty())
|
||||
{
|
||||
invalidate_regs.push_back (Args::StringToUInt32 (value_pair.first.str().c_str()));
|
||||
}
|
||||
} while (!value_pair.second.empty());
|
||||
}
|
||||
}
|
||||
|
||||
reg_info.byte_offset = reg_offset;
|
||||
assert (reg_info.byte_size != 0);
|
||||
reg_offset += reg_info.byte_size;
|
||||
if (!value_regs.empty())
|
||||
{
|
||||
value_regs.push_back(LLDB_INVALID_REGNUM);
|
||||
reg_info.value_regs = value_regs.data();
|
||||
}
|
||||
if (!invalidate_regs.empty())
|
||||
{
|
||||
invalidate_regs.push_back(LLDB_INVALID_REGNUM);
|
||||
reg_info.invalidate_regs = invalidate_regs.data();
|
||||
}
|
||||
|
||||
m_register_info.AddRegister(reg_info, reg_name, alt_name, set_name);
|
||||
}
|
||||
}
|
||||
|
|
@ -415,11 +454,6 @@ ProcessGDBRemote::BuildDynamicRegisterInfo (bool force)
|
|||
m_register_info.HardcodeARMRegisters(from_scratch);
|
||||
}
|
||||
|
||||
// Add some convenience registers (eax, ebx, ecx, edx, esi, edi, ebp, esp) to x86_64.
|
||||
if ((target_arch.IsValid() && target_arch.GetMachine() == llvm::Triple::x86_64)
|
||||
|| (remote_arch.IsValid() && remote_arch.GetMachine() == llvm::Triple::x86_64))
|
||||
m_register_info.Addx86_64ConvenienceRegisters();
|
||||
|
||||
// At this point, we can finalize our register info.
|
||||
m_register_info.Finalize ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -230,6 +230,8 @@ struct DNBRegisterInfo
|
|||
uint32_t reg_dwarf; // DWARF register number (INVALID_NUB_REGNUM when none)
|
||||
uint32_t reg_generic; // Generic register number (INVALID_NUB_REGNUM when none)
|
||||
uint32_t reg_gdb; // The GDB register number (INVALID_NUB_REGNUM when none)
|
||||
uint32_t *pseudo_regs; // If this register is a part of another register, list the one or more registers
|
||||
uint32_t *update_regs; // If modifying this register will invalidate other registers, list them here
|
||||
};
|
||||
|
||||
struct DNBRegisterSetInfo
|
||||
|
|
|
|||
|
|
@ -995,6 +995,58 @@ enum
|
|||
gpr_cs,
|
||||
gpr_fs,
|
||||
gpr_gs,
|
||||
gpr_eax,
|
||||
gpr_ebx,
|
||||
gpr_ecx,
|
||||
gpr_edx,
|
||||
gpr_edi,
|
||||
gpr_esi,
|
||||
gpr_ebp,
|
||||
gpr_esp,
|
||||
gpr_r8d, // Low 32 bits or r8
|
||||
gpr_r9d, // Low 32 bits or r9
|
||||
gpr_r10d, // Low 32 bits or r10
|
||||
gpr_r11d, // Low 32 bits or r11
|
||||
gpr_r12d, // Low 32 bits or r12
|
||||
gpr_r13d, // Low 32 bits or r13
|
||||
gpr_r14d, // Low 32 bits or r14
|
||||
gpr_r15d, // Low 32 bits or r15
|
||||
gpr_ax ,
|
||||
gpr_bx ,
|
||||
gpr_cx ,
|
||||
gpr_dx ,
|
||||
gpr_di ,
|
||||
gpr_si ,
|
||||
gpr_bp ,
|
||||
gpr_sp ,
|
||||
gpr_r8w, // Low 16 bits or r8
|
||||
gpr_r9w, // Low 16 bits or r9
|
||||
gpr_r10w, // Low 16 bits or r10
|
||||
gpr_r11w, // Low 16 bits or r11
|
||||
gpr_r12w, // Low 16 bits or r12
|
||||
gpr_r13w, // Low 16 bits or r13
|
||||
gpr_r14w, // Low 16 bits or r14
|
||||
gpr_r15w, // Low 16 bits or r15
|
||||
gpr_ah ,
|
||||
gpr_bh ,
|
||||
gpr_ch ,
|
||||
gpr_dh ,
|
||||
gpr_al ,
|
||||
gpr_bl ,
|
||||
gpr_cl ,
|
||||
gpr_dl ,
|
||||
gpr_dil,
|
||||
gpr_sil,
|
||||
gpr_bpl,
|
||||
gpr_spl,
|
||||
gpr_r8l, // Low 8 bits or r8
|
||||
gpr_r9l, // Low 8 bits or r9
|
||||
gpr_r10l, // Low 8 bits or r10
|
||||
gpr_r11l, // Low 8 bits or r11
|
||||
gpr_r12l, // Low 8 bits or r12
|
||||
gpr_r13l, // Low 8 bits or r13
|
||||
gpr_r14l, // Low 8 bits or r14
|
||||
gpr_r15l, // Low 8 bits or r15
|
||||
k_num_gpr_regs
|
||||
};
|
||||
|
||||
|
|
@ -1230,12 +1282,52 @@ enum gdb_regnums
|
|||
// register offset, encoding, format and native register. This ensures that
|
||||
// the register state structures are defined correctly and have the correct
|
||||
// sizes and offsets.
|
||||
#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg }
|
||||
#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg }
|
||||
#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg }
|
||||
#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg }
|
||||
#define DEFINE_GPR(reg) { e_regSetGPR, gpr_##reg, #reg, NULL, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, INVALID_NUB_REGNUM, gdb_##reg, NULL, NULL }
|
||||
#define DEFINE_GPR_ALT(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), gcc_dwarf_##reg, gcc_dwarf_##reg, gen, gdb_##reg, NULL, NULL }
|
||||
#define DEFINE_GPR_ALT2(reg, alt) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gdb_##reg, NULL, NULL }
|
||||
#define DEFINE_GPR_ALT3(reg, alt, gen) { e_regSetGPR, gpr_##reg, #reg, alt, Uint, Hex, GPR_SIZE(reg), GPR_OFFSET(reg), INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, gen, gdb_##reg, NULL, NULL }
|
||||
|
||||
#define DEFINE_GPR_PSEUDO_32(reg32,reg64) { e_regSetGPR, gpr_##reg32, #reg32, NULL, Uint, Hex, 4, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
|
||||
#define DEFINE_GPR_PSEUDO_16(reg16,reg64) { e_regSetGPR, gpr_##reg16, #reg16, NULL, Uint, Hex, 2, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
|
||||
#define DEFINE_GPR_PSEUDO_8H(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg64)+1,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
|
||||
#define DEFINE_GPR_PSEUDO_8L(reg8,reg64) { e_regSetGPR, gpr_##reg8 , #reg8 , NULL, Uint, Hex, 1, GPR_OFFSET(reg64) ,INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM, g_contained_##reg64, g_invalidate_##reg64 }
|
||||
|
||||
// General purpose registers for 64 bit
|
||||
|
||||
uint32_t g_contained_rax[] = { gpr_rax, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rbx[] = { gpr_rbx, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rcx[] = { gpr_rcx, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rdx[] = { gpr_rdx, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rdi[] = { gpr_rdi, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rsi[] = { gpr_rsi, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rbp[] = { gpr_rbp, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_rsp[] = { gpr_rsp, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r8[] = { gpr_r8 , INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r9[] = { gpr_r9 , INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r10[] = { gpr_r10, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r11[] = { gpr_r11, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r12[] = { gpr_r12, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r13[] = { gpr_r13, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r14[] = { gpr_r14, INVALID_NUB_REGNUM };
|
||||
uint32_t g_contained_r15[] = { gpr_r15, INVALID_NUB_REGNUM };
|
||||
|
||||
uint32_t g_invalidate_rax[] = { gpr_rax, gpr_eax , gpr_ax , gpr_ah , gpr_al, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rbx[] = { gpr_rbx, gpr_ebx , gpr_bx , gpr_bh , gpr_bl, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rcx[] = { gpr_rcx, gpr_ecx , gpr_cx , gpr_ch , gpr_cl, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rdx[] = { gpr_rdx, gpr_edx , gpr_dx , gpr_dh , gpr_dl, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rdi[] = { gpr_rdi, gpr_edi , gpr_di , gpr_dil , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rsi[] = { gpr_rsi, gpr_esi , gpr_si , gpr_sil , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rbp[] = { gpr_rbp, gpr_ebp , gpr_bp , gpr_bpl , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_rsp[] = { gpr_rsp, gpr_esp , gpr_sp , gpr_spl , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r8 [] = { gpr_r8 , gpr_r8d , gpr_r8w , gpr_r8l , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r9 [] = { gpr_r9 , gpr_r9d , gpr_r9w , gpr_r9l , INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r10[] = { gpr_r10, gpr_r10d, gpr_r10w, gpr_r10l, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r11[] = { gpr_r11, gpr_r11d, gpr_r11w, gpr_r11l, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r12[] = { gpr_r12, gpr_r12d, gpr_r12w, gpr_r12l, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r13[] = { gpr_r13, gpr_r13d, gpr_r13w, gpr_r13l, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r14[] = { gpr_r14, gpr_r14d, gpr_r14w, gpr_r14l, INVALID_NUB_REGNUM };
|
||||
uint32_t g_invalidate_r15[] = { gpr_r15, gpr_r15d, gpr_r15w, gpr_r15l, INVALID_NUB_REGNUM };
|
||||
|
||||
const DNBRegisterInfo
|
||||
DNBArchImplX86_64::g_gpr_registers[] =
|
||||
{
|
||||
|
|
@ -1260,106 +1352,158 @@ DNBArchImplX86_64::g_gpr_registers[] =
|
|||
DEFINE_GPR_ALT2 (cs, NULL),
|
||||
DEFINE_GPR_ALT2 (fs, NULL),
|
||||
DEFINE_GPR_ALT2 (gs, NULL),
|
||||
DEFINE_GPR_PSEUDO_32 (eax, rax),
|
||||
DEFINE_GPR_PSEUDO_32 (ebx, rbx),
|
||||
DEFINE_GPR_PSEUDO_32 (ecx, rcx),
|
||||
DEFINE_GPR_PSEUDO_32 (edx, rdx),
|
||||
DEFINE_GPR_PSEUDO_32 (edi, rdi),
|
||||
DEFINE_GPR_PSEUDO_32 (esi, rsi),
|
||||
DEFINE_GPR_PSEUDO_32 (ebp, rbp),
|
||||
DEFINE_GPR_PSEUDO_32 (esp, rsp),
|
||||
DEFINE_GPR_PSEUDO_32 (r8d, r8),
|
||||
DEFINE_GPR_PSEUDO_32 (r9d, r9),
|
||||
DEFINE_GPR_PSEUDO_32 (r10d, r10),
|
||||
DEFINE_GPR_PSEUDO_32 (r11d, r11),
|
||||
DEFINE_GPR_PSEUDO_32 (r12d, r12),
|
||||
DEFINE_GPR_PSEUDO_32 (r13d, r13),
|
||||
DEFINE_GPR_PSEUDO_32 (r14d, r14),
|
||||
DEFINE_GPR_PSEUDO_32 (r15d, r15),
|
||||
DEFINE_GPR_PSEUDO_16 (ax , rax),
|
||||
DEFINE_GPR_PSEUDO_16 (bx , rbx),
|
||||
DEFINE_GPR_PSEUDO_16 (cx , rcx),
|
||||
DEFINE_GPR_PSEUDO_16 (dx , rdx),
|
||||
DEFINE_GPR_PSEUDO_16 (di , rdi),
|
||||
DEFINE_GPR_PSEUDO_16 (si , rsi),
|
||||
DEFINE_GPR_PSEUDO_16 (bp , rbp),
|
||||
DEFINE_GPR_PSEUDO_16 (sp , rsp),
|
||||
DEFINE_GPR_PSEUDO_16 (r8w, r8),
|
||||
DEFINE_GPR_PSEUDO_16 (r9w, r9),
|
||||
DEFINE_GPR_PSEUDO_16 (r10w, r10),
|
||||
DEFINE_GPR_PSEUDO_16 (r11w, r11),
|
||||
DEFINE_GPR_PSEUDO_16 (r12w, r12),
|
||||
DEFINE_GPR_PSEUDO_16 (r13w, r13),
|
||||
DEFINE_GPR_PSEUDO_16 (r14w, r14),
|
||||
DEFINE_GPR_PSEUDO_16 (r15w, r15),
|
||||
DEFINE_GPR_PSEUDO_8H (ah , rax),
|
||||
DEFINE_GPR_PSEUDO_8H (bh , rbx),
|
||||
DEFINE_GPR_PSEUDO_8H (ch , rcx),
|
||||
DEFINE_GPR_PSEUDO_8H (dh , rdx),
|
||||
DEFINE_GPR_PSEUDO_8L (al , rax),
|
||||
DEFINE_GPR_PSEUDO_8L (bl , rbx),
|
||||
DEFINE_GPR_PSEUDO_8L (cl , rcx),
|
||||
DEFINE_GPR_PSEUDO_8L (dl , rdx),
|
||||
DEFINE_GPR_PSEUDO_8L (dil, rdi),
|
||||
DEFINE_GPR_PSEUDO_8L (sil, rsi),
|
||||
DEFINE_GPR_PSEUDO_8L (bpl, rbp),
|
||||
DEFINE_GPR_PSEUDO_8L (spl, rsp),
|
||||
DEFINE_GPR_PSEUDO_8L (r8l, r8),
|
||||
DEFINE_GPR_PSEUDO_8L (r9l, r9),
|
||||
DEFINE_GPR_PSEUDO_8L (r10l, r10),
|
||||
DEFINE_GPR_PSEUDO_8L (r11l, r11),
|
||||
DEFINE_GPR_PSEUDO_8L (r12l, r12),
|
||||
DEFINE_GPR_PSEUDO_8L (r13l, r13),
|
||||
DEFINE_GPR_PSEUDO_8L (r14l, r14),
|
||||
DEFINE_GPR_PSEUDO_8L (r15l, r15)
|
||||
};
|
||||
|
||||
// Floating point registers 64 bit
|
||||
const DNBRegisterInfo
|
||||
DNBArchImplX86_64::g_fpu_registers_no_avx[] =
|
||||
{
|
||||
{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , FPU_OFFSET(fcw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , FPU_OFFSET(fsw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , FPU_OFFSET(ftw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , FPU_OFFSET(fop) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , FPU_OFFSET(ip) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , FPU_OFFSET(cs) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , FPU_OFFSET(dp) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , FPU_OFFSET(ds) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , FPU_OFFSET(mxcsr) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , FPU_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
|
||||
{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0 },
|
||||
{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1 },
|
||||
{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2 },
|
||||
{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3 },
|
||||
{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4 },
|
||||
{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5 },
|
||||
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6 },
|
||||
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7 },
|
||||
{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), FPU_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), FPU_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), FPU_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), FPU_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), FPU_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), FPU_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), FPU_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), FPU_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7, NULL, NULL },
|
||||
|
||||
{ e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 },
|
||||
{ e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 },
|
||||
{ e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 },
|
||||
{ e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 },
|
||||
{ e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 },
|
||||
{ e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 },
|
||||
{ e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 },
|
||||
{ e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 },
|
||||
{ e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 },
|
||||
{ e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 },
|
||||
{ e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10 },
|
||||
{ e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11 },
|
||||
{ e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12 },
|
||||
{ e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13 },
|
||||
{ e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14 },
|
||||
{ e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15 },
|
||||
{ e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , FPU_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , FPU_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , FPU_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , FPU_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , FPU_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , FPU_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , FPU_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , FPU_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , FPU_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , FPU_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , FPU_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , FPU_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , FPU_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , FPU_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , FPU_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , FPU_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, NULL, NULL },
|
||||
};
|
||||
|
||||
const DNBRegisterInfo
|
||||
DNBArchImplX86_64::g_fpu_registers_avx[] =
|
||||
{
|
||||
{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetFPU, fpu_fcw , "fctrl" , NULL, Uint, Hex, FPU_SIZE_UINT(fcw) , AVX_OFFSET(fcw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_fsw , "fstat" , NULL, Uint, Hex, FPU_SIZE_UINT(fsw) , AVX_OFFSET(fsw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ftw , "ftag" , NULL, Uint, Hex, FPU_SIZE_UINT(ftw) , AVX_OFFSET(ftw) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_fop , "fop" , NULL, Uint, Hex, FPU_SIZE_UINT(fop) , AVX_OFFSET(fop) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ip , "fioff" , NULL, Uint, Hex, FPU_SIZE_UINT(ip) , AVX_OFFSET(ip) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_cs , "fiseg" , NULL, Uint, Hex, FPU_SIZE_UINT(cs) , AVX_OFFSET(cs) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_dp , "fooff" , NULL, Uint, Hex, FPU_SIZE_UINT(dp) , AVX_OFFSET(dp) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ds , "foseg" , NULL, Uint, Hex, FPU_SIZE_UINT(ds) , AVX_OFFSET(ds) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_mxcsr , "mxcsr" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsr) , AVX_OFFSET(mxcsr) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_mxcsrmask, "mxcsrmask" , NULL, Uint, Hex, FPU_SIZE_UINT(mxcsrmask) , AVX_OFFSET(mxcsrmask) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
|
||||
{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0 },
|
||||
{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1 },
|
||||
{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2 },
|
||||
{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3 },
|
||||
{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4 },
|
||||
{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5 },
|
||||
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6 },
|
||||
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7 },
|
||||
{ e_regSetFPU, fpu_stmm0, "stmm0", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm0), AVX_OFFSET(stmm0), gcc_dwarf_stmm0, gcc_dwarf_stmm0, -1U, gdb_stmm0, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm1, "stmm1", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm1), AVX_OFFSET(stmm1), gcc_dwarf_stmm1, gcc_dwarf_stmm1, -1U, gdb_stmm1, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm2, "stmm2", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm2), AVX_OFFSET(stmm2), gcc_dwarf_stmm2, gcc_dwarf_stmm2, -1U, gdb_stmm2, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm3, "stmm3", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm3), AVX_OFFSET(stmm3), gcc_dwarf_stmm3, gcc_dwarf_stmm3, -1U, gdb_stmm3, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm4, "stmm4", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm4), AVX_OFFSET(stmm4), gcc_dwarf_stmm4, gcc_dwarf_stmm4, -1U, gdb_stmm4, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm5, "stmm5", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm5), AVX_OFFSET(stmm5), gcc_dwarf_stmm5, gcc_dwarf_stmm5, -1U, gdb_stmm5, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm6, "stmm6", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm6), AVX_OFFSET(stmm6), gcc_dwarf_stmm6, gcc_dwarf_stmm6, -1U, gdb_stmm6, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_stmm7, "stmm7", NULL, Vector, VectorOfUInt8, FPU_SIZE_MMST(stmm7), AVX_OFFSET(stmm7), gcc_dwarf_stmm7, gcc_dwarf_stmm7, -1U, gdb_stmm7, NULL, NULL },
|
||||
|
||||
{ e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 },
|
||||
{ e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 },
|
||||
{ e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 },
|
||||
{ e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 },
|
||||
{ e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 },
|
||||
{ e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 },
|
||||
{ e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 },
|
||||
{ e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 },
|
||||
{ e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 },
|
||||
{ e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 },
|
||||
{ e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10 },
|
||||
{ e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11 },
|
||||
{ e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12 },
|
||||
{ e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13 },
|
||||
{ e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14 },
|
||||
{ e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15 },
|
||||
{ e_regSetFPU, fpu_xmm0 , "xmm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm0) , AVX_OFFSET(xmm0) , gcc_dwarf_xmm0 , gcc_dwarf_xmm0 , -1U, gdb_xmm0 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm1 , "xmm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm1) , AVX_OFFSET(xmm1) , gcc_dwarf_xmm1 , gcc_dwarf_xmm1 , -1U, gdb_xmm1 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm2 , "xmm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm2) , AVX_OFFSET(xmm2) , gcc_dwarf_xmm2 , gcc_dwarf_xmm2 , -1U, gdb_xmm2 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm3 , "xmm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm3) , AVX_OFFSET(xmm3) , gcc_dwarf_xmm3 , gcc_dwarf_xmm3 , -1U, gdb_xmm3 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm4 , "xmm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm4) , AVX_OFFSET(xmm4) , gcc_dwarf_xmm4 , gcc_dwarf_xmm4 , -1U, gdb_xmm4 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm5 , "xmm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm5) , AVX_OFFSET(xmm5) , gcc_dwarf_xmm5 , gcc_dwarf_xmm5 , -1U, gdb_xmm5 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm6 , "xmm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm6) , AVX_OFFSET(xmm6) , gcc_dwarf_xmm6 , gcc_dwarf_xmm6 , -1U, gdb_xmm6 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm7 , "xmm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm7) , AVX_OFFSET(xmm7) , gcc_dwarf_xmm7 , gcc_dwarf_xmm7 , -1U, gdb_xmm7 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm8 , "xmm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm8) , AVX_OFFSET(xmm8) , gcc_dwarf_xmm8 , gcc_dwarf_xmm8 , -1U, gdb_xmm8 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm9 , "xmm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm9) , AVX_OFFSET(xmm9) , gcc_dwarf_xmm9 , gcc_dwarf_xmm9 , -1U, gdb_xmm9 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm10, "xmm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm10) , AVX_OFFSET(xmm10), gcc_dwarf_xmm10, gcc_dwarf_xmm10, -1U, gdb_xmm10, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm11, "xmm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm11) , AVX_OFFSET(xmm11), gcc_dwarf_xmm11, gcc_dwarf_xmm11, -1U, gdb_xmm11, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm12, "xmm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm12) , AVX_OFFSET(xmm12), gcc_dwarf_xmm12, gcc_dwarf_xmm12, -1U, gdb_xmm12, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm13, "xmm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm13) , AVX_OFFSET(xmm13), gcc_dwarf_xmm13, gcc_dwarf_xmm13, -1U, gdb_xmm13, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm14, "xmm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm14) , AVX_OFFSET(xmm14), gcc_dwarf_xmm14, gcc_dwarf_xmm14, -1U, gdb_xmm14, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_xmm15, "xmm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_XMM(xmm15) , AVX_OFFSET(xmm15), gcc_dwarf_xmm15, gcc_dwarf_xmm15, -1U, gdb_xmm15, NULL, NULL },
|
||||
|
||||
{ e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1U, gdb_ymm0 },
|
||||
{ e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1U, gdb_ymm1 },
|
||||
{ e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1U, gdb_ymm2 },
|
||||
{ e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1U, gdb_ymm3 },
|
||||
{ e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1U, gdb_ymm4 },
|
||||
{ e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1U, gdb_ymm5 },
|
||||
{ e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1U, gdb_ymm6 },
|
||||
{ e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1U, gdb_ymm7 },
|
||||
{ e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1U, gdb_ymm8 },
|
||||
{ e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1U, gdb_ymm9 },
|
||||
{ e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1U, gdb_ymm10 },
|
||||
{ e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1U, gdb_ymm11 },
|
||||
{ e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1U, gdb_ymm12 },
|
||||
{ e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1U, gdb_ymm13 },
|
||||
{ e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1U, gdb_ymm14 },
|
||||
{ e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1U, gdb_ymm15 }
|
||||
{ e_regSetFPU, fpu_ymm0 , "ymm0" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm0) , AVX_OFFSET_YMM(0) , gcc_dwarf_ymm0 , gcc_dwarf_ymm0 , -1U, gdb_ymm0, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm1 , "ymm1" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm1) , AVX_OFFSET_YMM(1) , gcc_dwarf_ymm1 , gcc_dwarf_ymm1 , -1U, gdb_ymm1, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm2 , "ymm2" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm2) , AVX_OFFSET_YMM(2) , gcc_dwarf_ymm2 , gcc_dwarf_ymm2 , -1U, gdb_ymm2, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm3 , "ymm3" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm3) , AVX_OFFSET_YMM(3) , gcc_dwarf_ymm3 , gcc_dwarf_ymm3 , -1U, gdb_ymm3, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm4 , "ymm4" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm4) , AVX_OFFSET_YMM(4) , gcc_dwarf_ymm4 , gcc_dwarf_ymm4 , -1U, gdb_ymm4, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm5 , "ymm5" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm5) , AVX_OFFSET_YMM(5) , gcc_dwarf_ymm5 , gcc_dwarf_ymm5 , -1U, gdb_ymm5, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm6 , "ymm6" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm6) , AVX_OFFSET_YMM(6) , gcc_dwarf_ymm6 , gcc_dwarf_ymm6 , -1U, gdb_ymm6, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm7 , "ymm7" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm7) , AVX_OFFSET_YMM(7) , gcc_dwarf_ymm7 , gcc_dwarf_ymm7 , -1U, gdb_ymm7, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm8 , "ymm8" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm8) , AVX_OFFSET_YMM(8) , gcc_dwarf_ymm8 , gcc_dwarf_ymm8 , -1U, gdb_ymm8 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm9 , "ymm9" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm9) , AVX_OFFSET_YMM(9) , gcc_dwarf_ymm9 , gcc_dwarf_ymm9 , -1U, gdb_ymm9 , NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm10, "ymm10" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm10) , AVX_OFFSET_YMM(10), gcc_dwarf_ymm10, gcc_dwarf_ymm10, -1U, gdb_ymm10, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm11, "ymm11" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm11) , AVX_OFFSET_YMM(11), gcc_dwarf_ymm11, gcc_dwarf_ymm11, -1U, gdb_ymm11, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm12, "ymm12" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm12) , AVX_OFFSET_YMM(12), gcc_dwarf_ymm12, gcc_dwarf_ymm12, -1U, gdb_ymm12, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm13, "ymm13" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm13) , AVX_OFFSET_YMM(13), gcc_dwarf_ymm13, gcc_dwarf_ymm13, -1U, gdb_ymm13, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm14, "ymm14" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm14) , AVX_OFFSET_YMM(14), gcc_dwarf_ymm14, gcc_dwarf_ymm14, -1U, gdb_ymm14, NULL, NULL },
|
||||
{ e_regSetFPU, fpu_ymm15, "ymm15" , NULL, Vector, VectorOfUInt8, FPU_SIZE_YMM(ymm15) , AVX_OFFSET_YMM(15), gcc_dwarf_ymm15, gcc_dwarf_ymm15, -1U, gdb_ymm15, NULL, NULL }
|
||||
};
|
||||
|
||||
// Exception registers
|
||||
|
|
@ -1367,9 +1511,9 @@ DNBArchImplX86_64::g_fpu_registers_avx[] =
|
|||
const DNBRegisterInfo
|
||||
DNBArchImplX86_64::g_exc_registers[] =
|
||||
{
|
||||
{ e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1U, -1U, -1U, -1U },
|
||||
{ e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1U, -1U, -1U, -1U }
|
||||
{ e_regSetEXC, exc_trapno, "trapno" , NULL, Uint, Hex, EXC_SIZE (trapno) , EXC_OFFSET (trapno) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetEXC, exc_err, "err" , NULL, Uint, Hex, EXC_SIZE (err) , EXC_OFFSET (err) , -1U, -1U, -1U, -1U, NULL, NULL },
|
||||
{ e_regSetEXC, exc_faultvaddr, "faultvaddr", NULL, Uint, Hex, EXC_SIZE (faultvaddr), EXC_OFFSET (faultvaddr) , -1U, -1U, -1U, -1U, NULL, NULL }
|
||||
};
|
||||
|
||||
// Number of registers in each register set
|
||||
|
|
|
|||
|
|
@ -1552,6 +1552,30 @@ RNBRemote::HandlePacket_qRegisterInfo (const char *p)
|
|||
case GENERIC_REGNUM_ARG8: ostrm << "generic:arg8;"; break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
if (reg_entry->nub_info.pseudo_regs && reg_entry->nub_info.pseudo_regs[0] != INVALID_NUB_REGNUM)
|
||||
{
|
||||
ostrm << "container-regs:";
|
||||
for (unsigned i=0; reg_entry->nub_info.pseudo_regs[i] != INVALID_NUB_REGNUM; ++i)
|
||||
{
|
||||
if (i > 0)
|
||||
ostrm << ',';
|
||||
ostrm << DECIMAL << reg_entry->nub_info.pseudo_regs[i];
|
||||
}
|
||||
ostrm << ';';
|
||||
}
|
||||
|
||||
if (reg_entry->nub_info.update_regs && reg_entry->nub_info.update_regs[0] != INVALID_NUB_REGNUM)
|
||||
{
|
||||
ostrm << "invalidate-regs:";
|
||||
for (unsigned i=0; reg_entry->nub_info.update_regs[i] != INVALID_NUB_REGNUM; ++i)
|
||||
{
|
||||
if (i > 0)
|
||||
ostrm << ',';
|
||||
ostrm << DECIMAL << reg_entry->nub_info.update_regs[i];
|
||||
}
|
||||
ostrm << ';';
|
||||
}
|
||||
|
||||
return SendPacket (ostrm.str ());
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue