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Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emitted 

when shift amount is larger than 32.

llvm-svn: 143990
This commit is contained in:
Akira Hatanaka 2011-11-07 19:01:49 +00:00
parent 770f0646db
commit cf7e5b0976
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/Mips/Mips64InstrInfo.td
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@ -155,9 +155,9 @@ def : Pat<(i64 immZExt16:$in),
(ORi64 ZERO_64, imm:$in)>;
// zextloadi32_u
def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64_P8 addr:$a), 32), 32)>,
def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>,
Requires<[IsN64]>;
def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>,
Requires<[NotN64]>;
// hi/lo relocs