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[mips] Add tail call instructions. 

llvm-svn: 166338
This commit is contained in:
Akira Hatanaka 2012-10-19 21:14:34 +00:00
parent 0c5e357d87
commit d03d68a3ba
2 changed files with 12 additions and 0 deletions
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1
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -177,6 +177,7 @@ def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
} }
let DecoderNamespace = "Mips64" in let DecoderNamespace = "Mips64" in
def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>; def JALR64 : JumpLinkReg<0x00, 0x09, "jalr", CPU64Regs>;
def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, IsTailCall;
let DecoderNamespace = "Mips64" in { let DecoderNamespace = "Mips64" in {
/// Multiply and Divide Instructions. /// Multiply and Divide Instructions.

11
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -191,6 +191,15 @@ class IsCall {
bit isCall = 1; bit isCall = 1;
} }
class IsTailCall {
bit isCall = 1;
bit isTerminator = 1;
bit isReturn = 1;
bit isBarrier = 1;
bit hasExtraSrcRegAllocReq = 1;
bit isCodeGenOnly = 1;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction format superclass // Instruction format superclass
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@ -1013,6 +1022,8 @@ def JAL : JumpLink<0x03, "jal">;
def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
def TAILCALL : JumpFJ<0x02, "j", br>, IsTailCall;
def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
def RET : RetBase<CPURegs>; def RET : RetBase<CPURegs>;