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LegalizeIntegerTypes: Reorder operations in the "big shift by small amount" optimization, making the lives of later passes easier. 

llvm-svn: 151722
This commit is contained in:
Benjamin Kramer 2012-02-29 13:27:00 +00:00
parent 06af2bbb04
commit d05a0c6c42
2 changed files with 8 additions and 8 deletions
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8
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1419,10 +1419,10 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
std::swap(InL, InH); std::swap(InL, InH);
// Use a little trick to get the bits that move from Lo to Hi. First // Use a little trick to get the bits that move from Lo to Hi. First
// calculate the shift with amount-1. // shift by one bit.
SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, Amt2); SDValue Sh1 = DAG.getNode(Op2, dl, NVT, InL, DAG.getConstant(1, ShTy));
// Then shift one bit further to get the right result. // Then compute the remaining shift with amount-1.
SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, DAG.getConstant(1, ShTy)); SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2);
Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt); Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt);
Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2); Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2);

8
llvm/test/CodeGen/X86/legalize-shift-64.ll
View File

@ -8,9 +8,9 @@ define i64 @test1(i32 %xx, i32 %test) nounwind {
ret i64 %shl ret i64 %shl
; CHECK: test1: ; CHECK: test1:
; CHECK: shll %cl, %eax ; CHECK: shll %cl, %eax
; CHECK: shrl %edx
; CHECK: xorb $31 ; CHECK: xorb $31
; CHECK: shrl %cl, %edx ; CHECK: shrl %cl, %edx
; CHECK: shrl %edx
} }
define i64 @test2(i64 %xx, i32 %test) nounwind { define i64 @test2(i64 %xx, i32 %test) nounwind {
@ -20,9 +20,9 @@ define i64 @test2(i64 %xx, i32 %test) nounwind {
ret i64 %shl ret i64 %shl
; CHECK: test2: ; CHECK: test2:
; CHECK: shll %cl, %esi ; CHECK: shll %cl, %esi
; CHECK: shrl %edx
; CHECK: xorb $31 ; CHECK: xorb $31
; CHECK: shrl %cl, %edx ; CHECK: shrl %cl, %edx
; CHECK: shrl %edx
; CHECK: orl %esi, %edx ; CHECK: orl %esi, %edx
; CHECK: shll %cl, %eax ; CHECK: shll %cl, %eax
} }
@ -34,9 +34,9 @@ define i64 @test3(i64 %xx, i32 %test) nounwind {
ret i64 %shr ret i64 %shr
; CHECK: test3: ; CHECK: test3:
; CHECK: shrl %cl, %esi ; CHECK: shrl %cl, %esi
; CHECK: leal (%edx,%edx), %eax
; CHECK: xorb $31, %cl ; CHECK: xorb $31, %cl
; CHECK: shll %cl, %eax ; CHECK: shll %cl, %eax
; CHECK: addl %eax, %eax
; CHECK: orl %esi, %eax ; CHECK: orl %esi, %eax
; CHECK: shrl %cl, %edx ; CHECK: shrl %cl, %edx
} }
@ -48,9 +48,9 @@ define i64 @test4(i64 %xx, i32 %test) nounwind {
ret i64 %shr ret i64 %shr
; CHECK: test4: ; CHECK: test4:
; CHECK: shrl %cl, %esi ; CHECK: shrl %cl, %esi
; CHECK: leal (%edx,%edx), %eax
; CHECK: xorb $31, %cl ; CHECK: xorb $31, %cl
; CHECK: shll %cl, %eax ; CHECK: shll %cl, %eax
; CHECK: addl %eax, %eax
; CHECK: orl %esi, %eax ; CHECK: orl %esi, %eax
; CHECK: sarl %cl, %edx ; CHECK: sarl %cl, %edx
} }