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[ARM] Flag vcvt{t,b} with an f16 type specifier as part of the FP16 extension 

Additionally correct the Cortex-R7 definition to allow the FP16 feature.

llvm-svn: 254900
This commit is contained in:
Bradley Smith 2015-12-07 10:54:36 +00:00
parent b825de17b7
commit d5a1f47a63
4 changed files with 28 additions and 5 deletions
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1
llvm/lib/Target/ARM/ARM.td
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@ -585,6 +585,7 @@ def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
FeatureVFP3, FeatureVFP3,
FeatureVFPOnlySP, FeatureVFPOnlySP,
FeatureD16, FeatureD16,
FeatureFP16,
FeatureMP, FeatureMP,
FeatureSlowFPBrcc, FeatureSlowFPBrcc,
FeatureHWDivARM, FeatureHWDivARM,

12
llvm/lib/Target/ARM/ARMInstrVFP.td
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@ -540,19 +540,23 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
// FIXME: Verify encoding after integrated assembler is working. // FIXME: Verify encoding after integrated assembler is working.
def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm", /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>,
Requires<[HasFP16]>;
def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm", /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>,
Requires<[HasFP16]>;
def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm", /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>,
Requires<[HasFP16]>;
def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
[/* For disassembly only; pattern left blank */]>; [/* For disassembly only; pattern left blank */]>,
Requires<[HasFP16]>;
def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
(outs DPR:$Dd), (ins SPR:$Sm), (outs DPR:$Dd), (ins SPR:$Sm),

2
llvm/test/CodeGen/ARM/build-attributes.ll
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@ -1105,7 +1105,7 @@
; CORTEX-R7: .eabi_attribute 25, 1 ; CORTEX-R7: .eabi_attribute 25, 1
; CORTEX-R7: .eabi_attribute 27, 1 ; CORTEX-R7: .eabi_attribute 27, 1
; CORTEX-R7-NOT: .eabi_attribute 28 ; CORTEX-R7-NOT: .eabi_attribute 28
; CORTEX-R7-NOT: .eabi_attribute 36 ; CORTEX-R7: .eabi_attribute 36, 1
; CORTEX-R7: .eabi_attribute 38, 1 ; CORTEX-R7: .eabi_attribute 38, 1
; CORTEX-R7: .eabi_attribute 42, 1 ; CORTEX-R7: .eabi_attribute 42, 1
; CORTEX-R7: .eabi_attribute 44, 2 ; CORTEX-R7: .eabi_attribute 44, 2

18
llvm/test/MC/ARM/neon-vcvt-fp16.s Normal file
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@ -0,0 +1,18 @@
@ RUN: llvm-mc -mcpu=cortex-r7 -triple arm -show-encoding < %s 2>&1| \
@ RUN: FileCheck %s --check-prefix=CHECK-FP16
@ RUN: not llvm-mc -mcpu=cortex-r5 -triple arm -show-encoding < %s 2>&1 | \
@ RUN: FileCheck %s --check-prefix=CHECK-NOFP16
@ CHECK-FP16: vcvtt.f32.f16 s7, s1 @ encoding: [0xe0,0x3a,0xf2,0xee]
@ CHECK-NOFP16: instruction requires: half-float conversions
vcvtt.f32.f16 s7, s1
@ CHECK-FP16: vcvtt.f16.f32 s1, s7 @ encoding: [0xe3,0x0a,0xf3,0xee]
@ CHECK-NOFP16: instruction requires: half-float conversions
vcvtt.f16.f32 s1, s7
@ CHECK-FP16: vcvtb.f32.f16 s7, s1 @ encoding: [0x60,0x3a,0xf2,0xee]
@ CHECK-NOFP16: instruction requires: half-float conversions
vcvtb.f32.f16 s7, s1
@ CHECK-FP16: vcvtb.f16.f32 s1, s7 @ encoding: [0x63,0x0a,0xf3,0xee]
@ CHECK-NOFP16: instruction requires: half-float conversions
vcvtb.f16.f32 s1, s7