forked from OSchip/llvm-project
[NFC][InstCombine] Shift amount reassociation: can have trunc between shl's
https://rise4fun.com/Alive/OQbM Not so simple for lshr/ashr, so those maybe later. https://bugs.llvm.org/show_bug.cgi?id=42391 llvm-svn: 367189
This commit is contained in:
Roman Lebedev
parent
45d910de99
commit
d5bc4b09f1
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; Given pattern:
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; (trunc (x << Q) to iDst) << K
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; we should rewrite it as
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; (trunc (x << (Q+K)) to iDst) iff (Q+K) u< iDst
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; This is only valid for shl.
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; THIS FOLD DOES *NOT* REQUIRE ANY 'nuw'/`nsw` FLAGS!
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; Basic scalar test
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define i16 @t0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t0(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -2
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define <2 x i16> @t1_vec_splat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t1_vec_splat(
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; CHECK-NEXT: [[T0:%.*]] = sub <2 x i16> <i16 32, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -2, i16 -2>
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; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 32>, %y
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%t1 = zext <2 x i16> %t0 to <2 x i32>
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%t2 = shl <2 x i32> %x, %t1
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%t3 = trunc <2 x i32> %t2 to <2 x i16>
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%t4 = add <2 x i16> %y, <i16 -2, i16 -2>
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%t5 = shl <2 x i16> %t3, %t4
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ret <2 x i16> %t5
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}
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define <2 x i16> @t2_vec_nonsplat(<2 x i32> %x, <2 x i16> %y) {
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; CHECK-LABEL: @t2_vec_nonsplat(
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; CHECK-NEXT: [[T0:%.*]] = sub <2 x i16> <i16 32, i16 30>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <2 x i16> [[T0]] to <2 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <2 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <2 x i32> [[T2]] to <2 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <2 x i16> [[Y]], <i16 -2, i16 0>
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; CHECK-NEXT: [[T5:%.*]] = shl <2 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: ret <2 x i16> [[T5]]
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;
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%t0 = sub <2 x i16> <i16 32, i16 30>, %y
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%t1 = zext <2 x i16> %t0 to <2 x i32>
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%t2 = shl <2 x i32> %x, %t1
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%t3 = trunc <2 x i32> %t2 to <2 x i16>
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%t4 = add <2 x i16> %y, <i16 -2, i16 0>
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%t5 = shl <2 x i16> %t3, %t4
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ret <2 x i16> %t5
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}
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; Basic vector tests
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define <3 x i16> @t3_vec_nonsplat_undef0(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t3_vec_nonsplat_undef0(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -2, i16 -2, i16 -2>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -2, i16 -2, i16 -2>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t4_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t4_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 32, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -2, i16 undef, i16 -2>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 32, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -2, i16 undef, i16 -2>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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define <3 x i16> @t5_vec_nonsplat_undef1(<3 x i32> %x, <3 x i16> %y) {
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; CHECK-LABEL: @t5_vec_nonsplat_undef1(
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; CHECK-NEXT: [[T0:%.*]] = sub <3 x i16> <i16 32, i16 undef, i16 32>, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext <3 x i16> [[T0]] to <3 x i32>
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; CHECK-NEXT: [[T2:%.*]] = shl <3 x i32> [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc <3 x i32> [[T2]] to <3 x i16>
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; CHECK-NEXT: [[T4:%.*]] = add <3 x i16> [[Y]], <i16 -2, i16 undef, i16 -2>
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; CHECK-NEXT: [[T5:%.*]] = shl <3 x i16> [[T3]], [[T4]]
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; CHECK-NEXT: ret <3 x i16> [[T5]]
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;
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%t0 = sub <3 x i16> <i16 32, i16 undef, i16 32>, %y
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%t1 = zext <3 x i16> %t0 to <3 x i32>
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%t2 = shl <3 x i32> %x, %t1
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%t3 = trunc <3 x i32> %t2 to <3 x i16>
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%t4 = add <3 x i16> %y, <i16 -2, i16 undef, i16 -2>
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%t5 = shl <3 x i16> %t3, %t4
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ret <3 x i16> %t5
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}
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; One-use tests
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declare void @use16(i16)
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declare void @use32(i32)
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define i16 @t6_extrause0(i32 %x, i16 %y) {
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; CHECK-LABEL: @t6_extrause0(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -2
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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call void @use32(i32 %t2)
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t7_extrause1(i32 %x, i16 %y) {
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; CHECK-LABEL: @t7_extrause1(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -2
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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call void @use16(i16 %t3)
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%t4 = add i16 %y, -2
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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define i16 @t8_extrause2(i32 %x, i16 %y) {
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; CHECK-LABEL: @t8_extrause2(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: call void @use32(i32 [[T2]])
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: call void @use16(i16 [[T3]])
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; CHECK-NEXT: [[T4:%.*]] = add i16 [[Y]], -2
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; CHECK-NEXT: [[T5:%.*]] = shl i16 [[T3]], [[T4]]
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; CHECK-NEXT: ret i16 [[T5]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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call void @use32(i32 %t2)
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%t3 = trunc i32 %t2 to i16
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call void @use16(i16 %t3)
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%t4 = add i16 %y, -2
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%t5 = shl i16 %t3, %t4
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ret i16 %t5
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}
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; Special test
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; New shift amount is less than bitwidth after truncation, so we could pre-truncated.
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define i16 @t9_pretrunc(i32 %x, i16 %y) {
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; CHECK-LABEL: @t9_pretrunc(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: ret i16 [[T3]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -18
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%t5 = shl i16 %t3, %t4
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ret i16 %t3
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}
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; No 'nuw'/'nsw' flags are to be propagated!
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define i16 @t10_no_flags(i32 %x, i16 %y) {
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; CHECK-LABEL: @t10_no_flags(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl nuw nsw i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: ret i16 [[T3]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl nuw nsw i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = shl nuw nsw i16 %t3, %t4
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ret i16 %t3
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}
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; Negative tests
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; As-is this is not correct for other shift opcodes.
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define i16 @t11_shl(i32 %x, i16 %y) {
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; CHECK-LABEL: @t11_shl(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = lshr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: ret i16 [[T3]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = lshr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = lshr i16 %t3, %t4
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ret i16 %t3
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}
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define i16 @t12_ashr(i32 %x, i16 %y) {
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; CHECK-LABEL: @t12_ashr(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 32, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = ashr i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: ret i16 [[T3]]
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;
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%t0 = sub i16 32, %y
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%t1 = zext i16 %t0 to i32
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%t2 = ashr i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = ashr i16 %t3, %t4
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ret i16 %t3
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}
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; Can't fold, total shift would be 32
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define i16 @n13(i32 %x, i16 %y) {
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; CHECK-LABEL: @n13(
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; CHECK-NEXT: [[T0:%.*]] = sub i16 30, [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = zext i16 [[T0]] to i32
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; CHECK-NEXT: [[T2:%.*]] = shl i32 [[X:%.*]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = trunc i32 [[T2]] to i16
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; CHECK-NEXT: ret i16 [[T3]]
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;
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%t0 = sub i16 30, %y
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%t1 = zext i16 %t0 to i32
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%t2 = shl i32 %x, %t1
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%t3 = trunc i32 %t2 to i16
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%t4 = add i16 %y, -2
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%t5 = shl i16 %t3, %t4
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ret i16 %t3
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}
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