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[AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns 

llvm-svn: 334488
This commit is contained in:
Luke Geeson 2018-06-12 09:35:20 +00:00
parent 14db2509ac
commit dc82aa44e6
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/AArch64/AArch64InstrFormats.td
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@ -7938,10 +7938,10 @@ multiclass SIMDFPScalarRShift<bit U, bits<5> opc, string asm> {
let Inst{21-16} = imm{5-0}; let Inst{21-16} = imm{5-0};
let Inst{23-22} = 0b11; let Inst{23-22} = 0b11;
} }
def DHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?}, def DHr : BaseSIMDScalarShift<U, opc, {1,1,1,?,?,?,?},
FPR64, FPR16, vecshiftR64, asm, []> { FPR64, FPR16, vecshiftR64, asm, []> {
let Inst{21-16} = imm{5-0}; let Inst{21-16} = imm{5-0};
let Inst{23-22} = 0b11; let Inst{23-22} = 0b01;
let Inst{31} = 1; let Inst{31} = 1;
} }
def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?}, def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},