forked from OSchip/llvm-project
refactor .td files a bit, moving system instructions out to X86InstrSystem.td
llvm-svn: 115591
This commit is contained in:
Chris Lattner
parent
a992bbc08a
commit
dec85b8c64
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@ -116,13 +116,6 @@ def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
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Requires<[In64BitMode]>;
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Requires<[In64BitMode]>;
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}
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}
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// Interrupt Instructions
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def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
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Requires<[In64BitMode]>;
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def SYSRETQ : RI<0x07, RawFrm,
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(outs), (ins), "sysretq", []>, TB, Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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// Call Instructions...
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@ -330,9 +323,6 @@ def SCAS64 : RI<0xAF, RawFrm, (outs), (ins), "scasq", []>;
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def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
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def CMPS64 : RI<0xA7, RawFrm, (outs), (ins), "cmpsq", []>;
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// Fast system-call instructions
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def SYSEXIT64 : RI<0x35, RawFrm,
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(outs), (ins), "sysexit", []>, TB, Requires<[In64BitMode]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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// Move Instructions...
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@ -1742,28 +1732,6 @@ def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
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def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
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def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
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"push{q}\t%fs", []>, TB;
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def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
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"push{q}\t%gs", []>, TB;
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def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
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"pop{q}\t%fs", []>, TB;
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def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
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"pop{q}\t%gs", []>, TB;
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def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
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def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
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"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
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// Specialized register support
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// no m form encodable; use SMSW16m
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def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
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"smsw{q}\t$dst", []>, TB;
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// String manipulation instructions
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// String manipulation instructions
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@ -607,8 +607,8 @@ let mayLoad = 1 in
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def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16]
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(outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
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(outs), (ins i16mem:$dst), "fldcw\t$dst", []>;
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// Register free
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// FPU control instructions
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def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
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def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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"ffree\t$reg">, DD;
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"ffree\t$reg">, DD;
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@ -616,7 +616,8 @@ def FFREE : FPI<0xC0, AddRegFrm, (outs), (ins RST:$reg),
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def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
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def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", []>, DB;
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// Operandless floating-point instructions for the disassembler
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// Operandless floating-point instructions for the disassembler.
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def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
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def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
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def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", []>, D9;
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def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
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def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", []>, D9;
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@ -1,4 +1,4 @@
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//===----------------------------------------------------------------------===//
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//===- X86InstrInfo.td - Main X86 Instruction Definition ---*- tablegen -*-===//
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//
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//
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// The LLVM Compiler Infrastructure
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// The LLVM Compiler Infrastructure
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//
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//
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@ -501,7 +501,7 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
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}]>;
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}]>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction list...
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// Instruction list.
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//
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//
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// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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// ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
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@ -555,17 +555,6 @@ let neverHasSideEffects = 1 in {
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"nop{l}\t$zero", []>, TB;
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"nop{l}\t$zero", []>, TB;
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}
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}
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// Trap
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let Uses = [EFLAGS] in {
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def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
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}
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def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
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[(int_x86_int (i8 3))]>;
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def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
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[(int_x86_int imm:$trap)]>;
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def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
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def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
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// PIC base construction. This expands to code that looks like this:
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// PIC base construction. This expands to code that looks like this:
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// call $next_inst
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// call $next_inst
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// popl %destreg"
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// popl %destreg"
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@ -922,81 +911,9 @@ def CMPS8 : I<0xA6, RawFrm, (outs), (ins), "cmps{b}", []>;
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def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
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def CMPS16 : I<0xA7, RawFrm, (outs), (ins), "cmps{w}", []>, OpSize;
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def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
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def CMPS32 : I<0xA7, RawFrm, (outs), (ins), "cmps{l}", []>;
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let Defs = [RAX, RDX] in
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def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
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TB;
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let Defs = [RAX, RCX, RDX] in
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def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
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let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
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}
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def SYSCALL : I<0x05, RawFrm,
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(outs), (ins), "syscall", []>, TB;
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def SYSRETL : I<0x07, RawFrm,
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(outs), (ins), "sysretl", []>, TB;
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def SYSENTER : I<0x34, RawFrm,
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(outs), (ins), "sysenter", []>, TB;
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def SYSEXIT : I<0x35, RawFrm,
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(outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
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def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", []>;
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Input/Output Instructions...
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// Move Instructions.
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//
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let Defs = [AL], Uses = [DX] in
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def IN8rr : I<0xEC, RawFrm, (outs), (ins),
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"in{b}\t{%dx, %al|%AL, %DX}", []>;
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let Defs = [AX], Uses = [DX] in
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def IN16rr : I<0xED, RawFrm, (outs), (ins),
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"in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
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let Defs = [EAX], Uses = [DX] in
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def IN32rr : I<0xED, RawFrm, (outs), (ins),
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"in{l}\t{%dx, %eax|%EAX, %DX}", []>;
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let Defs = [AL] in
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def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
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"in{b}\t{$port, %al|%AL, $port}", []>;
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let Defs = [AX] in
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def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
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let Defs = [EAX] in
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def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
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"in{l}\t{$port, %eax|%EAX, $port}", []>;
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let Uses = [DX, AL] in
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def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
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"out{b}\t{%al, %dx|%DX, %AL}", []>;
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let Uses = [DX, AX] in
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def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
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"out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
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let Uses = [DX, EAX] in
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def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
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"out{l}\t{%eax, %dx|%DX, %EAX}", []>;
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let Uses = [AL] in
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def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
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"out{b}\t{%al, $port|$port, %AL}", []>;
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let Uses = [AX] in
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def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
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let Uses = [EAX] in
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def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
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"out{l}\t{%eax, $port|$port, %EAX}", []>;
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def IN8 : I<0x6C, RawFrm, (outs), (ins),
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"ins{b}", []>;
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def IN16 : I<0x6D, RawFrm, (outs), (ins),
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"ins{w}", []>, OpSize;
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def IN32 : I<0x6D, RawFrm, (outs), (ins),
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"ins{l}", []>;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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//
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//
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let neverHasSideEffects = 1 in {
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let neverHasSideEffects = 1 in {
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def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
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def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
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@ -4195,138 +4112,6 @@ def ATOMSWAP6432 : I<0, Pseudo, (outs GR32:$dst1, GR32:$dst2),
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"#ATOMSWAP6432 PSEUDO!", []>;
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"#ATOMSWAP6432 PSEUDO!", []>;
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}
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}
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// Segmentation support instructions.
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def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
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def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
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"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
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def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
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def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
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def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
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"str{w}\t{$dst}", []>, TB;
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def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
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"str{w}\t{$dst}", []>, TB;
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def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
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"ltr{w}\t{$src}", []>, TB;
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def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
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"ltr{w}\t{$src}", []>, TB;
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def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
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"push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
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"push{l}\t%cs", []>, Requires<[In32BitMode]>;
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def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
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"push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
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"push{l}\t%ss", []>, Requires<[In32BitMode]>;
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def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
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"push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
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"push{l}\t%ds", []>, Requires<[In32BitMode]>;
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def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
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"push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
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def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
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"push{l}\t%es", []>, Requires<[In32BitMode]>;
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def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
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"push{w}\t%fs", []>, OpSize, TB;
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def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
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"push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
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def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
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"push{w}\t%gs", []>, OpSize, TB;
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def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
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"push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
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// No "pop cs" instruction.
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def POPSS16 : I<0x17, RawFrm, (outs), (ins),
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"pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
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def POPSS32 : I<0x17, RawFrm, (outs), (ins),
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"pop{l}\t%ss", []> , Requires<[In32BitMode]>;
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def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
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"pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
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def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
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"pop{l}\t%ds", []> , Requires<[In32BitMode]>;
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def POPES16 : I<0x07, RawFrm, (outs), (ins),
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"pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
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def POPES32 : I<0x07, RawFrm, (outs), (ins),
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"pop{l}\t%es", []> , Requires<[In32BitMode]>;
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def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
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|
||||||
"pop{w}\t%fs", []>, OpSize, TB;
|
|
||||||
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
|
||||||
"pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
|
|
||||||
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
|
||||||
"pop{w}\t%gs", []>, OpSize, TB;
|
|
||||||
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
|
||||||
"pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
|
|
||||||
|
|
||||||
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|
||||||
"lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|
||||||
def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|
||||||
"lds{l}\t{$src, $dst|$dst, $src}", []>;
|
|
||||||
def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|
||||||
"lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
||||||
def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|
||||||
"lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
||||||
def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|
||||||
"les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
|
||||||
def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|
||||||
"les{l}\t{$src, $dst|$dst, $src}", []>;
|
|
||||||
def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|
||||||
"lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
||||||
def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|
||||||
"lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
||||||
def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
|
||||||
"lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
|
||||||
def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
|
||||||
"lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
|
||||||
|
|
||||||
def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
|
|
||||||
"verr\t$seg", []>, TB;
|
|
||||||
def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
|
|
||||||
"verr\t$seg", []>, TB;
|
|
||||||
def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
|
|
||||||
"verw\t$seg", []>, TB;
|
|
||||||
def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
|
||||||
"verw\t$seg", []>, TB;
|
|
||||||
|
|
||||||
// Descriptor-table support instructions
|
|
||||||
|
|
||||||
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
|
||||||
"sgdt\t$dst", []>, TB;
|
|
||||||
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
|
||||||
"sidt\t$dst", []>, TB;
|
|
||||||
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
|
||||||
"sldt{w}\t$dst", []>, TB, OpSize;
|
|
||||||
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
|
||||||
"sldt{w}\t$dst", []>, TB;
|
|
||||||
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
|
||||||
"sldt{l}\t$dst", []>, TB;
|
|
||||||
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
|
||||||
"lgdt\t$src", []>, TB;
|
|
||||||
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
|
||||||
"lidt\t$src", []>, TB;
|
|
||||||
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
|
||||||
"lldt{w}\t$src", []>, TB;
|
|
||||||
def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
|
||||||
"lldt{w}\t$src", []>, TB;
|
|
||||||
|
|
||||||
// Lock instruction prefix
|
// Lock instruction prefix
|
||||||
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
|
def LOCK_PREFIX : I<0xF0, RawFrm, (outs), (ins), "lock", []>;
|
||||||
|
|
||||||
|
|
@ -4339,13 +4124,6 @@ def REP_PREFIX : I<0xF3, RawFrm, (outs), (ins), "rep", []>;
|
||||||
def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
|
def REPNE_PREFIX : I<0xF2, RawFrm, (outs), (ins), "repne", []>;
|
||||||
}
|
}
|
||||||
|
|
||||||
// Segment override instruction prefixes
|
|
||||||
def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
|
|
||||||
def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
|
|
||||||
def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
|
|
||||||
def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
|
|
||||||
def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
|
|
||||||
def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
|
|
||||||
|
|
||||||
// String manipulation instructions
|
// String manipulation instructions
|
||||||
|
|
||||||
|
|
@ -4357,17 +4135,8 @@ def OUTSB : I<0x6E, RawFrm, (outs), (ins), "outsb", []>;
|
||||||
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
|
def OUTSW : I<0x6F, RawFrm, (outs), (ins), "outsw", []>, OpSize;
|
||||||
def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
|
def OUTSD : I<0x6F, RawFrm, (outs), (ins), "outs{l|d}", []>;
|
||||||
|
|
||||||
// CPU flow control instructions
|
|
||||||
|
|
||||||
def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
|
|
||||||
def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
|
|
||||||
|
|
||||||
// FPU control instructions
|
|
||||||
|
|
||||||
def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", []>, DB;
|
|
||||||
|
|
||||||
// Flag instructions
|
// Flag instructions
|
||||||
|
|
||||||
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
|
def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>;
|
||||||
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
|
def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>;
|
||||||
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
|
def CLI : I<0xFA, RawFrm, (outs), (ins), "cli", []>;
|
||||||
|
|
@ -4379,35 +4148,9 @@ def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>;
|
||||||
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
|
def CLTS : I<0x06, RawFrm, (outs), (ins), "clts", []>, TB;
|
||||||
|
|
||||||
// Table lookup instructions
|
// Table lookup instructions
|
||||||
|
|
||||||
def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
|
def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>;
|
||||||
|
|
||||||
// Specialized register support
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
|
||||||
def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
|
||||||
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
|
||||||
|
|
||||||
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
|
||||||
"smsw{w}\t$dst", []>, OpSize, TB;
|
|
||||||
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
|
||||||
"smsw{l}\t$dst", []>, TB;
|
|
||||||
// For memory operands, there is only a 16-bit form
|
|
||||||
def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
|
|
||||||
"smsw{w}\t$dst", []>, TB;
|
|
||||||
|
|
||||||
def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
|
||||||
"lmsw{w}\t$src", []>, TB;
|
|
||||||
def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
|
||||||
"lmsw{w}\t$src", []>, TB;
|
|
||||||
|
|
||||||
def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
|
||||||
|
|
||||||
// Cache instructions
|
|
||||||
|
|
||||||
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
|
||||||
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
|
|
||||||
|
|
||||||
// VMX instructions
|
// VMX instructions
|
||||||
|
|
||||||
// 66 0F 38 80
|
// 66 0F 38 80
|
||||||
|
|
@ -4962,39 +4705,25 @@ def : Pat<(and GR32:$src1, i32immSExt8:$src2),
|
||||||
(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
(AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
// Floating Point Stack Support
|
// Subsystems.
|
||||||
//===----------------------------------------------------------------------===//
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
// Floating Point Stack Support
|
||||||
include "X86InstrFPStack.td"
|
include "X86InstrFPStack.td"
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
// X86-64 Support
|
// X86-64 Support
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
include "X86Instr64bit.td"
|
include "X86Instr64bit.td"
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
// SIMD support (SSE, MMX and AVX)
|
// SIMD support (SSE, MMX and AVX)
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
include "X86InstrFragmentsSIMD.td"
|
include "X86InstrFragmentsSIMD.td"
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
// FMA - Fused Multiply-Add support (requires FMA)
|
// FMA - Fused Multiply-Add support (requires FMA)
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
include "X86InstrFMA.td"
|
include "X86InstrFMA.td"
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
// SSE, MMX and 3DNow! vector support.
|
||||||
// XMM Floating point support (requires SSE / SSE2)
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
include "X86InstrSSE.td"
|
include "X86InstrSSE.td"
|
||||||
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
// MMX and XMM Packed Integer support (requires MMX, SSE, and SSE2)
|
|
||||||
//===----------------------------------------------------------------------===//
|
|
||||||
|
|
||||||
include "X86InstrMMX.td"
|
include "X86InstrMMX.td"
|
||||||
include "X86Instr3DNow.td"
|
include "X86Instr3DNow.td"
|
||||||
|
|
||||||
|
// System instructions.
|
||||||
|
include "X86InstrSystem.td"
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,303 @@
|
||||||
|
//===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
|
||||||
|
//
|
||||||
|
// The LLVM Compiler Infrastructure
|
||||||
|
//
|
||||||
|
// This file is distributed under the University of Illinois Open Source
|
||||||
|
// License. See LICENSE.TXT for details.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
//
|
||||||
|
// This file describes the X86 instructions that are generally used in
|
||||||
|
// privileged modes. These are not typically used by the compiler, but are
|
||||||
|
// supported for the assembler and disassembler.
|
||||||
|
//
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
|
||||||
|
let Defs = [RAX, RDX] in
|
||||||
|
def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>,
|
||||||
|
TB;
|
||||||
|
|
||||||
|
let Defs = [RAX, RCX, RDX] in
|
||||||
|
def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
|
||||||
|
|
||||||
|
// CPU flow control instructions
|
||||||
|
|
||||||
|
let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
|
||||||
|
def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
|
||||||
|
}
|
||||||
|
|
||||||
|
def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
|
||||||
|
def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
|
||||||
|
|
||||||
|
// Interrupt and SysCall Instructions.
|
||||||
|
let Uses = [EFLAGS] in
|
||||||
|
def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
|
||||||
|
def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
|
||||||
|
[(int_x86_int (i8 3))]>;
|
||||||
|
def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
|
||||||
|
[(int_x86_int imm:$trap)]>;
|
||||||
|
|
||||||
|
def SYSCALL : I<0x05, RawFrm,
|
||||||
|
(outs), (ins), "syscall", []>, TB;
|
||||||
|
def SYSRETL : I<0x07, RawFrm,
|
||||||
|
(outs), (ins), "sysretl", []>, TB;
|
||||||
|
def SYSRETQ : RI<0x07, RawFrm,
|
||||||
|
(outs), (ins), "sysretq", []>, TB, Requires<[In64BitMode]>;
|
||||||
|
|
||||||
|
def SYSENTER : I<0x34, RawFrm,
|
||||||
|
(outs), (ins), "sysenter", []>, TB;
|
||||||
|
def SYSEXIT : I<0x35, RawFrm,
|
||||||
|
(outs), (ins), "sysexit", []>, TB, Requires<[In32BitMode]>;
|
||||||
|
|
||||||
|
def SYSEXIT64 : RI<0x35, RawFrm,
|
||||||
|
(outs), (ins), "sysexit", []>, TB, Requires<[In64BitMode]>;
|
||||||
|
|
||||||
|
def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
|
||||||
|
def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
|
||||||
|
def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
|
||||||
|
Requires<[In64BitMode]>;
|
||||||
|
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Input/Output Instructions.
|
||||||
|
//
|
||||||
|
let Defs = [AL], Uses = [DX] in
|
||||||
|
def IN8rr : I<0xEC, RawFrm, (outs), (ins),
|
||||||
|
"in{b}\t{%dx, %al|%AL, %DX}", []>;
|
||||||
|
let Defs = [AX], Uses = [DX] in
|
||||||
|
def IN16rr : I<0xED, RawFrm, (outs), (ins),
|
||||||
|
"in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
|
||||||
|
let Defs = [EAX], Uses = [DX] in
|
||||||
|
def IN32rr : I<0xED, RawFrm, (outs), (ins),
|
||||||
|
"in{l}\t{%dx, %eax|%EAX, %DX}", []>;
|
||||||
|
|
||||||
|
let Defs = [AL] in
|
||||||
|
def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"in{b}\t{$port, %al|%AL, $port}", []>;
|
||||||
|
let Defs = [AX] in
|
||||||
|
def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
|
||||||
|
let Defs = [EAX] in
|
||||||
|
def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"in{l}\t{$port, %eax|%EAX, $port}", []>;
|
||||||
|
|
||||||
|
let Uses = [DX, AL] in
|
||||||
|
def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
|
||||||
|
"out{b}\t{%al, %dx|%DX, %AL}", []>;
|
||||||
|
let Uses = [DX, AX] in
|
||||||
|
def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
|
||||||
|
"out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
|
||||||
|
let Uses = [DX, EAX] in
|
||||||
|
def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
|
||||||
|
"out{l}\t{%eax, %dx|%DX, %EAX}", []>;
|
||||||
|
|
||||||
|
let Uses = [AL] in
|
||||||
|
def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"out{b}\t{%al, $port|$port, %AL}", []>;
|
||||||
|
let Uses = [AX] in
|
||||||
|
def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
|
||||||
|
let Uses = [EAX] in
|
||||||
|
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||||
|
"out{l}\t{%eax, $port|$port, %EAX}", []>;
|
||||||
|
|
||||||
|
def IN8 : I<0x6C, RawFrm, (outs), (ins),
|
||||||
|
"ins{b}", []>;
|
||||||
|
def IN16 : I<0x6D, RawFrm, (outs), (ins),
|
||||||
|
"ins{w}", []>, OpSize;
|
||||||
|
def IN32 : I<0x6D, RawFrm, (outs), (ins),
|
||||||
|
"ins{l}", []>;
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Segment override instruction prefixes
|
||||||
|
|
||||||
|
def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
|
||||||
|
def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
|
||||||
|
def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
|
||||||
|
def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
|
||||||
|
def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
|
||||||
|
def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
|
||||||
|
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Segmentation support instructions.
|
||||||
|
|
||||||
|
def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||||
|
"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||||
|
"lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
|
||||||
|
// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
|
||||||
|
def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
||||||
|
"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||||
|
"lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
|
||||||
|
def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||||
|
"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||||
|
"lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||||
|
"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||||
|
"lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
|
||||||
|
def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
|
||||||
|
|
||||||
|
def STRr : I<0x00, MRM1r, (outs GR16:$dst), (ins),
|
||||||
|
"str{w}\t{$dst}", []>, TB;
|
||||||
|
def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
|
||||||
|
"str{w}\t{$dst}", []>, TB;
|
||||||
|
def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
|
||||||
|
"ltr{w}\t{$src}", []>, TB;
|
||||||
|
def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
|
||||||
|
"ltr{w}\t{$src}", []>, TB;
|
||||||
|
|
||||||
|
def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%cs", []>, Requires<[In32BitMode]>, OpSize;
|
||||||
|
def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%cs", []>, Requires<[In32BitMode]>;
|
||||||
|
def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%ss", []>, Requires<[In32BitMode]>, OpSize;
|
||||||
|
def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%ss", []>, Requires<[In32BitMode]>;
|
||||||
|
def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%ds", []>, Requires<[In32BitMode]>, OpSize;
|
||||||
|
def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%ds", []>, Requires<[In32BitMode]>;
|
||||||
|
def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%es", []>, Requires<[In32BitMode]>, OpSize;
|
||||||
|
def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%es", []>, Requires<[In32BitMode]>;
|
||||||
|
|
||||||
|
def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%fs", []>, OpSize, TB;
|
||||||
|
def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%fs", []>, TB, Requires<[In32BitMode]>;
|
||||||
|
def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
|
||||||
|
"push{w}\t%gs", []>, OpSize, TB;
|
||||||
|
def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
|
||||||
|
"push{l}\t%gs", []>, TB, Requires<[In32BitMode]>;
|
||||||
|
|
||||||
|
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
|
||||||
|
"push{q}\t%fs", []>, TB;
|
||||||
|
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
||||||
|
"push{q}\t%gs", []>, TB;
|
||||||
|
|
||||||
|
// No "pop cs" instruction.
|
||||||
|
def POPSS16 : I<0x17, RawFrm, (outs), (ins),
|
||||||
|
"pop{w}\t%ss", []>, OpSize, Requires<[In32BitMode]>;
|
||||||
|
def POPSS32 : I<0x17, RawFrm, (outs), (ins),
|
||||||
|
"pop{l}\t%ss", []> , Requires<[In32BitMode]>;
|
||||||
|
def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
|
||||||
|
"pop{w}\t%ds", []>, OpSize, Requires<[In32BitMode]>;
|
||||||
|
def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
|
||||||
|
"pop{l}\t%ds", []> , Requires<[In32BitMode]>;
|
||||||
|
def POPES16 : I<0x07, RawFrm, (outs), (ins),
|
||||||
|
"pop{w}\t%es", []>, OpSize, Requires<[In32BitMode]>;
|
||||||
|
def POPES32 : I<0x07, RawFrm, (outs), (ins),
|
||||||
|
"pop{l}\t%es", []> , Requires<[In32BitMode]>;
|
||||||
|
def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
|
||||||
|
"pop{w}\t%fs", []>, OpSize, TB;
|
||||||
|
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
||||||
|
"pop{l}\t%fs", []>, TB , Requires<[In32BitMode]>;
|
||||||
|
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
||||||
|
"pop{w}\t%gs", []>, OpSize, TB;
|
||||||
|
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
||||||
|
"pop{l}\t%gs", []>, TB , Requires<[In32BitMode]>;
|
||||||
|
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
|
||||||
|
"pop{q}\t%fs", []>, TB;
|
||||||
|
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
|
||||||
|
"pop{q}\t%gs", []>, TB;
|
||||||
|
|
||||||
|
|
||||||
|
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||||
|
"lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
||||||
|
def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||||
|
"lds{l}\t{$src, $dst|$dst, $src}", []>;
|
||||||
|
def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||||
|
"lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||||
|
"lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||||
|
"les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
|
||||||
|
def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||||
|
"les{l}\t{$src, $dst|$dst, $src}", []>;
|
||||||
|
def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||||
|
"lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||||
|
"lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||||
|
"lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
|
||||||
|
def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||||
|
"lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||||
|
"lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||||
|
"lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||||
|
"lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
|
||||||
|
|
||||||
|
|
||||||
|
def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
|
||||||
|
"verr\t$seg", []>, TB;
|
||||||
|
def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
|
||||||
|
"verr\t$seg", []>, TB;
|
||||||
|
def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
|
||||||
|
"verw\t$seg", []>, TB;
|
||||||
|
def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
||||||
|
"verw\t$seg", []>, TB;
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Descriptor-table support instructions
|
||||||
|
|
||||||
|
def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
||||||
|
"sgdt\t$dst", []>, TB;
|
||||||
|
def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
||||||
|
"sidt\t$dst", []>, TB;
|
||||||
|
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
||||||
|
"sldt{w}\t$dst", []>, TB, OpSize;
|
||||||
|
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
||||||
|
"sldt{w}\t$dst", []>, TB;
|
||||||
|
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
||||||
|
"sldt{l}\t$dst", []>, TB;
|
||||||
|
def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
||||||
|
"lgdt\t$src", []>, TB;
|
||||||
|
def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
||||||
|
"lidt\t$src", []>, TB;
|
||||||
|
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
||||||
|
"lldt{w}\t$src", []>, TB;
|
||||||
|
def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
|
||||||
|
"lldt{w}\t$src", []>, TB;
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Specialized register support
|
||||||
|
def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
|
||||||
|
def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
|
||||||
|
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
|
||||||
|
|
||||||
|
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
||||||
|
"smsw{w}\t$dst", []>, OpSize, TB;
|
||||||
|
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
||||||
|
"smsw{l}\t$dst", []>, TB;
|
||||||
|
|
||||||
|
// no m form encodable; use SMSW16m
|
||||||
|
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
||||||
|
"smsw{q}\t$dst", []>, TB;
|
||||||
|
|
||||||
|
// For memory operands, there is only a 16-bit form
|
||||||
|
def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
|
||||||
|
"smsw{w}\t$dst", []>, TB;
|
||||||
|
|
||||||
|
def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
|
||||||
|
"lmsw{w}\t$src", []>, TB;
|
||||||
|
def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
|
||||||
|
"lmsw{w}\t$src", []>, TB;
|
||||||
|
|
||||||
|
def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
|
||||||
|
|
||||||
|
//===----------------------------------------------------------------------===//
|
||||||
|
// Cache instructions
|
||||||
|
def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
|
||||||
|
def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
|
||||||
|
|
||||||
Loading…
Reference in New Issue