forked from OSchip/llvm-project
[SystemZ] A few fixes in scheduler files.
Review: U Weigand llvm-svn: 286362
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@ -527,7 +527,7 @@ def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
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// Load address extended
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def : InstRW<[LSU, FXa], (instregex "LAE(Y)?$")>;
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def : InstRW<[LSU, FXa, Lat5, BeginGroup], (instregex "LAE(Y)?$")>;
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// Load/store access multiple (not modeled precisely)
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
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@ -546,10 +546,10 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
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def : InstRW<[FXa, FXa, FXb, Lat5, GroupAlone], (instregex "BAL(R)?$")>;
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// Test addressing mode
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def : InstRW<[FXb, EndGroup], (instregex "TAM$")>;
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def : InstRW<[FXb], (instregex "TAM$")>;
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// Set addressing mode
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def : InstRW<[FXb, FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>;
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def : InstRW<[FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>;
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// Branch (and save) and set mode.
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def : InstRW<[FXa, FXb, Lat2, GroupAlone], (instregex "BSM$")>;
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@ -504,7 +504,7 @@ def : InstRW<[FXU, LSU, FXU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
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// Load address extended
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def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>;
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def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
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// Load/store access multiple (not modeled precisely)
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
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@ -523,14 +523,14 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
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// Test addressing mode
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def : InstRW<[FXU, EndGroup], (instregex "TAM$")>;
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def : InstRW<[FXU], (instregex "TAM$")>;
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// Set addressing mode
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def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
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// Branch (and save) and set mode.
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def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>;
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def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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@ -506,7 +506,7 @@ def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>;
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def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>;
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// Load address extended
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def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>;
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def : InstRW<[LSU, FXU, Lat5, GroupAlone], (instregex "LAE(Y)?$")>;
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// Load/store access multiple (not modeled precisely)
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def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>;
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@ -525,14 +525,14 @@ def : InstRW<[LSU, EndGroup], (instregex "SPM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>;
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// Test addressing mode
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def : InstRW<[FXU, EndGroup], (instregex "TAM$")>;
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def : InstRW<[FXU], (instregex "TAM$")>;
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// Set addressing mode
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def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>;
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// Branch (and save) and set mode.
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def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>;
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def : InstRW<[FXU, LSU, Lat5, GroupAlone], (instregex "BSM$")>;
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def : InstRW<[FXU, FXU, LSU, Lat6, GroupAlone], (instregex "BASSM$")>;
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//===----------------------------------------------------------------------===//
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// Transactional execution
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