forked from OSchip/llvm-project
[x86/SLH] Fix a bug where we would try to post-load harden non-GPRs.
Found cases that hit the assert I added. This patch factors the validity checking into a nice helper routine and calls it when deciding to harden post-load, and asserts it when doing so later. I've added tests for the various ways of loading a floating point type, as well as loading all vector permutations. Even though many of these go to identical instructions, it seems good to somewhat comprehensively test them. I'm confident there will be more fixes needed here, I'll try to add tests each time as I get this predicate adjusted. llvm-svn: 337160
This commit is contained in:
Chandler Carruth
parent
d1a381b17a
commit
e66a6f48e3
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@ -173,6 +173,7 @@ private:
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MachineInstr *
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sinkPostLoadHardenedInst(MachineInstr &MI,
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SmallPtrSetImpl<MachineInstr *> &HardenedLoads);
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bool canHardenPostLoad(MachineInstr &MI);
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void hardenPostLoad(MachineInstr &MI, MachineSSAUpdater &PredStateSSA);
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void checkReturnInstr(MachineInstr &MI, MachineSSAUpdater &PredStateSSA);
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void checkCallInstr(MachineInstr &MI, MachineSSAUpdater &PredStateSSA);
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@ -1115,12 +1116,12 @@ void X86SpeculativeLoadHardeningPass::checkAllLoads(
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(IndexReg && LoadDepRegs.test(IndexReg)))
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continue;
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// If post-load hardening is enabled, this load is known to be
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// data-invariant, and we aren't already going to harden one of the
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// If post-load hardening is enabled, this load is compatible with
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// post-load hardening, and we aren't already going to harden one of the
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// address registers, queue it up to be hardened post-load. Notably, even
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// once hardened this won't introduce a useful dependency that could prune
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// out subsequent loads.
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if (EnablePostLoadHardening && isDataInvariantLoad(MI) &&
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if (EnablePostLoadHardening && canHardenPostLoad(MI) &&
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!HardenedAddrRegs.count(BaseReg) &&
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!HardenedAddrRegs.count(IndexReg)) {
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HardenPostLoad.insert(&MI);
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@ -1602,6 +1603,25 @@ MachineInstr *X86SpeculativeLoadHardeningPass::sinkPostLoadHardenedInst(
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return MI;
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}
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bool X86SpeculativeLoadHardeningPass::canHardenPostLoad(MachineInstr &MI) {
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if (!isDataInvariantLoad(MI))
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return false;
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auto &DefOp = MI.getOperand(0);
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unsigned OldDefReg = DefOp.getReg();
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auto *DefRC = MRI->getRegClass(OldDefReg);
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int DefRegBytes = TRI->getRegSizeInBits(*DefRC) / 8;
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if (DefRegBytes > 8)
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// We don't support post-load hardening of vectors.
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return false;
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const TargetRegisterClass *GPRRegClasses[] = {
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&X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,
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&X86::GR64RegClass};
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return DefRC->hasSuperClassEq(GPRRegClasses[Log2_32(DefRegBytes)]);
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}
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// We can harden non-leaking loads into register without touching the address
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// by just hiding all of the loaded bits. We use an `or` instruction to do
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// this because having the poison value be all ones allows us to use the same
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@ -1609,8 +1629,8 @@ MachineInstr *X86SpeculativeLoadHardeningPass::sinkPostLoadHardenedInst(
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// execution and coercing them to one is sufficient.
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void X86SpeculativeLoadHardeningPass::hardenPostLoad(
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MachineInstr &MI, MachineSSAUpdater &PredStateSSA) {
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assert(isDataInvariantLoad(MI) &&
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"Cannot get here with a non-invariant load!");
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assert(canHardenPostLoad(MI) &&
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"Invalid instruction for post-load hardening!");
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc Loc = MI.getDebugLoc();
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@ -1625,14 +1645,6 @@ void X86SpeculativeLoadHardeningPass::hardenPostLoad(
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unsigned OrOpCodes[] = {X86::OR8rr, X86::OR16rr, X86::OR32rr, X86::OR64rr};
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unsigned OrOpCode = OrOpCodes[Log2_32(DefRegBytes)];
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#ifndef NDEBUG
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const TargetRegisterClass *OrRegClasses[] = {
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&X86::GR8RegClass, &X86::GR16RegClass, &X86::GR32RegClass,
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&X86::GR64RegClass};
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assert(DefRC->hasSuperClassEq(OrRegClasses[Log2_32(DefRegBytes)]) &&
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"Cannot define this register with OR instruction!");
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#endif
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unsigned SubRegImms[] = {X86::sub_8bit, X86::sub_16bit, X86::sub_32bit};
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auto GetStateRegInRC = [&](const TargetRegisterClass &RC) {
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@ -590,3 +590,275 @@ lpad:
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call void @sink(i32 %leak)
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unreachable
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}
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declare void @sink_float(float)
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declare void @sink_double(double)
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; Test direct and converting loads of floating point values.
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define void @test_fp_loads(float* %fptr, double* %dptr, i32* %i32ptr, i64* %i64ptr) nounwind {
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; X64-LABEL: test_fp_loads:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %r15
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; X64-NEXT: pushq %r14
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; X64-NEXT: pushq %r12
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; X64-NEXT: pushq %rbx
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; X64-NEXT: pushq %rax
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: movq %rcx, %r15
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; X64-NEXT: movq %rdx, %r14
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; X64-NEXT: movq %rsi, %rbx
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; X64-NEXT: movq %rdi, %r12
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; X64-NEXT: movq $-1, %rcx
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r12
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_float
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %rbx
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; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_double
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-NEXT: cvtsd2ss %xmm0, %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_float
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: cvtss2sd %xmm0, %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_double
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r14
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: cvtsi2ssl (%r14), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_float
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r15
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: cvtsi2sdq (%r15), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_double
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: cvtsi2ssq (%r15), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_float
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: xorps %xmm0, %xmm0
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; X64-NEXT: cvtsi2sdl (%r14), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_double
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: addq $8, %rsp
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; X64-NEXT: popq %rbx
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; X64-NEXT: popq %r12
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; X64-NEXT: popq %r14
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; X64-NEXT: popq %r15
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; X64-NEXT: retq
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;
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; X64-LFENCE-LABEL: test_fp_loads:
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; X64-LFENCE: # %bb.0: # %entry
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; X64-LFENCE-NEXT: pushq %r15
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; X64-LFENCE-NEXT: pushq %r14
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; X64-LFENCE-NEXT: pushq %r12
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; X64-LFENCE-NEXT: pushq %rbx
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; X64-LFENCE-NEXT: pushq %rax
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; X64-LFENCE-NEXT: movq %rcx, %r15
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; X64-LFENCE-NEXT: movq %rdx, %r14
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; X64-LFENCE-NEXT: movq %rsi, %rbx
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; X64-LFENCE-NEXT: movq %rdi, %r12
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; X64-LFENCE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-LFENCE-NEXT: callq sink_float
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; X64-LFENCE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-LFENCE-NEXT: callq sink_double
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; X64-LFENCE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; X64-LFENCE-NEXT: cvtsd2ss %xmm0, %xmm0
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; X64-LFENCE-NEXT: callq sink_float
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; X64-LFENCE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-LFENCE-NEXT: cvtss2sd %xmm0, %xmm0
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; X64-LFENCE-NEXT: callq sink_double
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; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
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; X64-LFENCE-NEXT: cvtsi2ssl (%r14), %xmm0
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; X64-LFENCE-NEXT: callq sink_float
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; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
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; X64-LFENCE-NEXT: cvtsi2sdq (%r15), %xmm0
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; X64-LFENCE-NEXT: callq sink_double
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; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
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; X64-LFENCE-NEXT: cvtsi2ssq (%r15), %xmm0
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; X64-LFENCE-NEXT: callq sink_float
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; X64-LFENCE-NEXT: xorps %xmm0, %xmm0
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; X64-LFENCE-NEXT: cvtsi2sdl (%r14), %xmm0
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; X64-LFENCE-NEXT: callq sink_double
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; X64-LFENCE-NEXT: addq $8, %rsp
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; X64-LFENCE-NEXT: popq %rbx
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; X64-LFENCE-NEXT: popq %r12
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; X64-LFENCE-NEXT: popq %r14
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; X64-LFENCE-NEXT: popq %r15
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; X64-LFENCE-NEXT: retq
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entry:
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%f1 = load float, float* %fptr
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call void @sink_float(float %f1)
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%d1 = load double, double* %dptr
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call void @sink_double(double %d1)
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%f2.d = load double, double* %dptr
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%f2 = fptrunc double %f2.d to float
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call void @sink_float(float %f2)
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%d2.f = load float, float* %fptr
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%d2 = fpext float %d2.f to double
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call void @sink_double(double %d2)
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%f3.i = load i32, i32* %i32ptr
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%f3 = sitofp i32 %f3.i to float
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call void @sink_float(float %f3)
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%d3.i = load i64, i64* %i64ptr
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%d3 = sitofp i64 %d3.i to double
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call void @sink_double(double %d3)
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%f4.i = load i64, i64* %i64ptr
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%f4 = sitofp i64 %f4.i to float
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call void @sink_float(float %f4)
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%d4.i = load i32, i32* %i32ptr
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%d4 = sitofp i32 %d4.i to double
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call void @sink_double(double %d4)
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ret void
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}
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declare void @sink_v4f32(<4 x float>)
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declare void @sink_v2f64(<2 x double>)
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declare void @sink_v16i8(<16 x i8>)
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declare void @sink_v8i16(<8 x i16>)
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declare void @sink_v4i32(<4 x i32>)
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declare void @sink_v2i64(<2 x i64>)
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; Test loads of vectors.
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define void @test_vec_loads(<4 x float>* %v4f32ptr, <2 x double>* %v2f64ptr, <16 x i8>* %v16i8ptr, <8 x i16>* %v8i16ptr, <4 x i32>* %v4i32ptr, <2 x i64>* %v2i64ptr) nounwind {
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; X64-LABEL: test_vec_loads:
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; X64: # %bb.0: # %entry
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; X64-NEXT: pushq %r15
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; X64-NEXT: pushq %r14
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; X64-NEXT: pushq %r13
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; X64-NEXT: pushq %r12
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; X64-NEXT: pushq %rbx
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: movq %r9, %r14
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; X64-NEXT: movq %r8, %r15
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; X64-NEXT: movq %rcx, %r12
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; X64-NEXT: movq %rdx, %r13
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; X64-NEXT: movq %rsi, %rbx
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; X64-NEXT: movq $-1, %rcx
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %rdi
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; X64-NEXT: movaps (%rdi), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v4f32
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %rbx
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; X64-NEXT: movaps (%rbx), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v2f64
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r13
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; X64-NEXT: movaps (%r13), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v16i8
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r12
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; X64-NEXT: movaps (%r12), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v8i16
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r15
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; X64-NEXT: movaps (%r15), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v4i32
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: orq %rax, %r14
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; X64-NEXT: movaps (%r14), %xmm0
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: callq sink_v2i64
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; X64-NEXT: movq %rsp, %rax
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; X64-NEXT: sarq $63, %rax
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; X64-NEXT: shlq $47, %rax
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; X64-NEXT: orq %rax, %rsp
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; X64-NEXT: popq %rbx
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; X64-NEXT: popq %r12
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; X64-NEXT: popq %r13
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; X64-NEXT: popq %r14
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; X64-NEXT: popq %r15
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; X64-NEXT: retq
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;
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; X64-LFENCE-LABEL: test_vec_loads:
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; X64-LFENCE: # %bb.0: # %entry
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; X64-LFENCE-NEXT: pushq %r15
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; X64-LFENCE-NEXT: pushq %r14
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; X64-LFENCE-NEXT: pushq %r13
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; X64-LFENCE-NEXT: pushq %r12
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; X64-LFENCE-NEXT: pushq %rbx
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; X64-LFENCE-NEXT: movq %r9, %r14
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; X64-LFENCE-NEXT: movq %r8, %r15
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; X64-LFENCE-NEXT: movq %rcx, %r12
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; X64-LFENCE-NEXT: movq %rdx, %r13
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; X64-LFENCE-NEXT: movq %rsi, %rbx
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; X64-LFENCE-NEXT: movaps (%rdi), %xmm0
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; X64-LFENCE-NEXT: callq sink_v4f32
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; X64-LFENCE-NEXT: movaps (%rbx), %xmm0
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; X64-LFENCE-NEXT: callq sink_v2f64
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; X64-LFENCE-NEXT: movaps (%r13), %xmm0
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; X64-LFENCE-NEXT: callq sink_v16i8
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; X64-LFENCE-NEXT: movaps (%r12), %xmm0
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; X64-LFENCE-NEXT: callq sink_v8i16
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; X64-LFENCE-NEXT: movaps (%r15), %xmm0
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; X64-LFENCE-NEXT: callq sink_v4i32
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; X64-LFENCE-NEXT: movaps (%r14), %xmm0
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; X64-LFENCE-NEXT: callq sink_v2i64
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; X64-LFENCE-NEXT: popq %rbx
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; X64-LFENCE-NEXT: popq %r12
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; X64-LFENCE-NEXT: popq %r13
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; X64-LFENCE-NEXT: popq %r14
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; X64-LFENCE-NEXT: popq %r15
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; X64-LFENCE-NEXT: retq
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entry:
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%x1 = load <4 x float>, <4 x float>* %v4f32ptr
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call void @sink_v4f32(<4 x float> %x1)
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%x2 = load <2 x double>, <2 x double>* %v2f64ptr
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call void @sink_v2f64(<2 x double> %x2)
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%x3 = load <16 x i8>, <16 x i8>* %v16i8ptr
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call void @sink_v16i8(<16 x i8> %x3)
|
||||
%x4 = load <8 x i16>, <8 x i16>* %v8i16ptr
|
||||
call void @sink_v8i16(<8 x i16> %x4)
|
||||
%x5 = load <4 x i32>, <4 x i32>* %v4i32ptr
|
||||
call void @sink_v4i32(<4 x i32> %x5)
|
||||
%x6 = load <2 x i64>, <2 x i64>* %v2i64ptr
|
||||
call void @sink_v2i64(<2 x i64> %x6)
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue