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Bring back 2>&1 redirection for this test 

llvm-svn: 295864
This commit is contained in:
Matthias Braun 2017-02-22 19:16:33 +00:00
parent 6bb79157dd
commit e8a0f5ef3b
1 changed files with 1 additions and 1 deletions
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llvm/test/CodeGen/Hexagon/expand-condsets-rm-reg.mir
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@ -1,4 +1,4 @@
# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets | FileCheck %s
# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s
# REQUIRES: asserts
# Check that coalesced registers are removed from live intervals.