wangtao
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

[AMDGPU] Fix double space in disassembly of some DPP instructions 

Differential Revision: https://reviews.llvm.org/D90373
This commit is contained in:
Jay Foad 2020-10-28 16:59:29 +00:00
parent dbae3d50f1
commit e9dd2c4fe2
5 changed files with 7340 additions and 7340 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

46
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
View File

@ -783,7 +783,7 @@ void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
unsigned Imm = MI->getOperand(OpNo).getImm();
O << " dpp8:[" << formatDec(Imm & 0x7);
O << "dpp8:[" << formatDec(Imm & 0x7);
for (size_t i = 1; i < 8; ++i) {
O << ',' << formatDec((Imm >> (3 * i)) & 0x7);
}
@ -797,81 +797,81 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
unsigned Imm = MI->getOperand(OpNo).getImm();
if (Imm <= DppCtrl::QUAD_PERM_LAST) {
O << " quad_perm:[";
O << "quad_perm:[";
O << formatDec(Imm & 0x3) << ',';
O << formatDec((Imm & 0xc) >> 2) << ',';
O << formatDec((Imm & 0x30) >> 4) << ',';
O << formatDec((Imm & 0xc0) >> 6) << ']';
} else if ((Imm >= DppCtrl::ROW_SHL_FIRST) &&
(Imm <= DppCtrl::ROW_SHL_LAST)) {
O << " row_shl:";
O << "row_shl:";
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= DppCtrl::ROW_SHR_FIRST) &&
(Imm <= DppCtrl::ROW_SHR_LAST)) {
O << " row_shr:";
O << "row_shr:";
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= DppCtrl::ROW_ROR_FIRST) &&
(Imm <= DppCtrl::ROW_ROR_LAST)) {
O << " row_ror:";
O << "row_ror:";
printU4ImmDecOperand(MI, OpNo, O);
} else if (Imm == DppCtrl::WAVE_SHL1) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* wave_shl is not supported starting from GFX10 */";
O << "/* wave_shl is not supported starting from GFX10 */";
return;
}
O << " wave_shl:1";
O << "wave_shl:1";
} else if (Imm == DppCtrl::WAVE_ROL1) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* wave_rol is not supported starting from GFX10 */";
O << "/* wave_rol is not supported starting from GFX10 */";
return;
}
O << " wave_rol:1";
O << "wave_rol:1";
} else if (Imm == DppCtrl::WAVE_SHR1) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* wave_shr is not supported starting from GFX10 */";
O << "/* wave_shr is not supported starting from GFX10 */";
return;
}
O << " wave_shr:1";
O << "wave_shr:1";
} else if (Imm == DppCtrl::WAVE_ROR1) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* wave_ror is not supported starting from GFX10 */";
O << "/* wave_ror is not supported starting from GFX10 */";
return;
}
O << " wave_ror:1";
O << "wave_ror:1";
} else if (Imm == DppCtrl::ROW_MIRROR) {
O << " row_mirror";
O << "row_mirror";
} else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
O << " row_half_mirror";
O << "row_half_mirror";
} else if (Imm == DppCtrl::BCAST15) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* row_bcast is not supported starting from GFX10 */";
O << "/* row_bcast is not supported starting from GFX10 */";
return;
}
O << " row_bcast:15";
O << "row_bcast:15";
} else if (Imm == DppCtrl::BCAST31) {
if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
O << " /* row_bcast is not supported starting from GFX10 */";
O << "/* row_bcast is not supported starting from GFX10 */";
return;
}
O << " row_bcast:31";
O << "row_bcast:31";
} else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
(Imm <= DppCtrl::ROW_SHARE_LAST)) {
if (!AMDGPU::isGFX10(STI)) {
O << " /* row_share is not supported on ASICs earlier than GFX10 */";
O << "/* row_share is not supported on ASICs earlier than GFX10 */";
return;
}
O << " row_share:";
O << "row_share:";
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
(Imm <= DppCtrl::ROW_XMASK_LAST)) {
if (!AMDGPU::isGFX10(STI)) {
O << " /* row_xmask is not supported on ASICs earlier than GFX10 */";
O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
return;
}
O << "row_xmask:";
printU4ImmDecOperand(MI, OpNo, O);
} else {
O << " /* Invalid dpp_ctrl value */";
O << "/* Invalid dpp_ctrl value */";
}
}

2
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -2022,7 +2022,7 @@ class getAsmDPP8 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT
string args = !if(!not(HasModifiers),
getAsm32<0, NumSrcArgs, DstVT>.ret,
", "#src0#src1);
string ret = dst#args#"$dpp8$fi";
string ret = dst#args#" $dpp8$fi";
}
class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {