forked from OSchip/llvm-project
SDAG: Implement Select instead of SelectImpl in HexagonDAGToDAGISel
- Where we were returning a node before, call ReplaceNode instead. - Where we had already replaced all uses and we returned a node, just remove the dead node instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. Part of llvm.org/pr26808. llvm-svn: 269358
This commit is contained in:
Justin Bogner
parent
d1dadf6bcf
commit
ec37a02766
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@ -70,7 +70,7 @@ public:
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virtual void PreprocessISelDAG() override;
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virtual void EmitFunctionEntryCode() override;
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SDNode *SelectImpl(SDNode *N) override;
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void Select(SDNode *N) override;
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// Complex Pattern Selectors.
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inline bool SelectAddrGA(SDValue &N, SDValue &R);
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@ -90,32 +90,30 @@ public:
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// intrinsic's functionality).
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SDNode *StoreInstrForLoadIntrinsic(MachineSDNode *LoadN, SDNode *IntN);
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SDNode *SelectFrameIndex(SDNode *N);
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void SelectFrameIndex(SDNode *N);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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SDNode *SelectLoadOfLoadIntrinsic(LoadSDNode *N);
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SDNode *SelectLoad(SDNode *N);
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SDNode *SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
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SDNode *SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
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SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
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SDLoc dl);
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SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
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SDLoc dl);
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SDNode *SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
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SDNode *SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
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SDNode *SelectStore(SDNode *N);
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SDNode *SelectSHL(SDNode *N);
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SDNode *SelectMul(SDNode *N);
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SDNode *SelectZeroExtend(SDNode *N);
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SDNode *SelectIntrinsicWChain(SDNode *N);
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SDNode *SelectIntrinsicWOChain(SDNode *N);
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SDNode *SelectConstant(SDNode *N);
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SDNode *SelectConstantFP(SDNode *N);
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SDNode *SelectAdd(SDNode *N);
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SDNode *SelectBitOp(SDNode *N);
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bool tryLoadOfLoadIntrinsic(LoadSDNode *N);
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void SelectLoad(SDNode *N);
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void SelectBaseOffsetLoad(LoadSDNode *LD, SDLoc dl);
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void SelectIndexedLoad(LoadSDNode *LD, SDLoc dl);
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void SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode, SDLoc dl);
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void SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode, SDLoc dl);
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void SelectBaseOffsetStore(StoreSDNode *ST, SDLoc dl);
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void SelectIndexedStore(StoreSDNode *ST, SDLoc dl);
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void SelectStore(SDNode *N);
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void SelectSHL(SDNode *N);
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void SelectMul(SDNode *N);
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void SelectZeroExtend(SDNode *N);
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void SelectIntrinsicWChain(SDNode *N);
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void SelectIntrinsicWOChain(SDNode *N);
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void SelectConstant(SDNode *N);
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void SelectConstantFP(SDNode *N);
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void SelectAdd(SDNode *N);
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void SelectBitOp(SDNode *N);
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// XformMskToBitPosU5Imm - Returns the bit position which
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// the single bit 32 bit mask represents.
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@ -259,9 +257,9 @@ static bool doesIntrinsicReturnPredicate(unsigned ID) {
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}
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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unsigned Opcode,
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SDLoc dl) {
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void HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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unsigned Opcode,
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SDLoc dl) {
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SDValue Chain = LD->getChain();
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EVT LoadedVT = LD->getMemoryVT();
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SDValue Base = LD->getBasePtr();
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@ -286,7 +284,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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SDValue(Result_1, 1),
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SDValue(Result_1, 2) };
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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@ -308,13 +307,12 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadSignExtend64(LoadSDNode *LD,
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SDValue(Result_3, 0),
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SDValue(Result_1, 1) };
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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CurDAG->RemoveDeadNode(LD);
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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unsigned Opcode,
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SDLoc dl) {
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void HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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unsigned Opcode,
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SDLoc dl) {
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SDValue Chain = LD->getChain();
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EVT LoadedVT = LD->getMemoryVT();
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SDValue Base = LD->getBasePtr();
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@ -342,7 +340,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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SDValue(Result_1, 1),
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SDValue(Result_1, 2) };
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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// Generate an indirect load.
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@ -369,11 +368,12 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoadZeroExtend64(LoadSDNode *LD,
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SDValue(Result_3, 0), // New address.
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SDValue(Result_1, 1) };
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ReplaceUses(Froms, Tos, 3);
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return Result_2;
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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void HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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SDValue Chain = LD->getChain();
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SDValue Base = LD->getBasePtr();
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SDValue Offset = LD->getOffset();
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@ -435,11 +435,15 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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llvm_unreachable("unknown memory type");
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// For zero extended i64 loads, we need to add combine instructions.
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if (LD->getValueType(0) == MVT::i64 && IsZeroExt)
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return SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
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if (LD->getValueType(0) == MVT::i64 && IsZeroExt) {
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SelectIndexedLoadZeroExtend64(LD, Opcode, dl);
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return;
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}
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// Handle sign extended i64 loads.
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if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
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return SelectIndexedLoadSignExtend64(LD, Opcode, dl);
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if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD) {
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SelectIndexedLoadSignExtend64(LD, Opcode, dl);
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return;
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}
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if (HII->isValidAutoIncImm(LoadedVT, Val)) {
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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@ -469,7 +473,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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};
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ReplaceUses(Froms, Tos, 3);
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}
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return Result;
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CurDAG->RemoveDeadNode(LD);
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return;
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} else {
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SDValue TargetConst0 = CurDAG->getTargetConstant(0, dl, MVT::i32);
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SDValue TargetConstVal = CurDAG->getTargetConstant(Val, dl, MVT::i32);
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@ -492,7 +497,8 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedLoad(LoadSDNode *LD, SDLoc dl) {
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SDValue(Result_1, 1)
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};
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ReplaceUses(Froms, Tos, 3);
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return Result_1;
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CurDAG->RemoveDeadNode(LD);
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return;
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}
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}
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@ -584,7 +590,7 @@ SDNode *HexagonDAGToDAGISel::StoreInstrForLoadIntrinsic(MachineSDNode *LoadN,
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return StoreN;
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}
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SDNode *HexagonDAGToDAGISel::SelectLoadOfLoadIntrinsic(LoadSDNode *N) {
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bool HexagonDAGToDAGISel::tryLoadOfLoadIntrinsic(LoadSDNode *N) {
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// The intrinsics for load circ/brev perform two operations:
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// 1. Load a value V from the specified location, using the addressing
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// mode corresponding to the intrinsic.
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@ -608,7 +614,7 @@ SDNode *HexagonDAGToDAGISel::SelectLoadOfLoadIntrinsic(LoadSDNode *N) {
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SDNode *C = Ch.getNode();
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if (C->getOpcode() != ISD::INTRINSIC_W_CHAIN)
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return nullptr;
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return false;
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// The second load can only be eliminated if its extension type matches
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// that of the load instruction corresponding to the intrinsic. The user
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@ -633,12 +639,12 @@ SDNode *HexagonDAGToDAGISel::SelectLoadOfLoadIntrinsic(LoadSDNode *N) {
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break;
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}
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if (N->getExtensionType() != IntExt)
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return nullptr;
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return false;
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// Make sure the target location for the loaded value in the load intrinsic
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// is the location from which LD (or N) is loading.
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if (C->getNumOperands() < 4 || Loc.getNode() != C->getOperand(3).getNode())
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return nullptr;
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return false;
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if (MachineSDNode *L = LoadInstrForLoadIntrinsic(C)) {
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SDNode *S = StoreInstrForLoadIntrinsic(L, C);
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@ -649,31 +655,33 @@ SDNode *HexagonDAGToDAGISel::SelectLoadOfLoadIntrinsic(LoadSDNode *N) {
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// the DAG, the selection code will see it again, but without the load,
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// and it will generate a store that is normally required for it.
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CurDAG->RemoveDeadNodes();
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return L;
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return true;
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}
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return nullptr;
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return false;
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}
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SDNode *HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
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void HexagonDAGToDAGISel::SelectLoad(SDNode *N) {
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SDLoc dl(N);
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LoadSDNode *LD = cast<LoadSDNode>(N);
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ISD::MemIndexedMode AM = LD->getAddressingMode();
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// Handle indexed loads.
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if (AM != ISD::UNINDEXED)
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return SelectIndexedLoad(LD, dl);
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if (AM != ISD::UNINDEXED) {
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SelectIndexedLoad(LD, dl);
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return;
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}
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// Handle patterns using circ/brev load intrinsics.
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if (SDNode *LI = SelectLoadOfLoadIntrinsic(LD))
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return LI;
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if (tryLoadOfLoadIntrinsic(LD))
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return;
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return SelectCode(LD);
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SelectCode(LD);
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}
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SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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void HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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SDValue Chain = ST->getChain();
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SDValue Base = ST->getBasePtr();
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SDValue Offset = ST->getOffset();
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@ -727,7 +735,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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ReplaceUses(ST, Result);
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ReplaceUses(SDValue(ST,1), SDValue(Result,1));
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CurDAG->RemoveDeadNode(ST);
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return nullptr;
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return;
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}
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// Note: Order of operands matches the def of instruction:
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@ -775,23 +783,24 @@ SDNode *HexagonDAGToDAGISel::SelectIndexedStore(StoreSDNode *ST, SDLoc dl) {
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ReplaceUses(SDValue(ST,0), SDValue(Result_2,0));
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ReplaceUses(SDValue(ST,1), SDValue(Result_1,0));
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CurDAG->RemoveDeadNode(ST);
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return nullptr;
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return;
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}
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SDNode *HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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void HexagonDAGToDAGISel::SelectStore(SDNode *N) {
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SDLoc dl(N);
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StoreSDNode *ST = cast<StoreSDNode>(N);
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ISD::MemIndexedMode AM = ST->getAddressingMode();
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// Handle indexed stores.
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if (AM != ISD::UNINDEXED) {
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return SelectIndexedStore(ST, dl);
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SelectIndexedStore(ST, dl);
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return;
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}
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return SelectCode(ST);
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SelectCode(ST);
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}
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SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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void HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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SDLoc dl(N);
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//
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@ -816,7 +825,8 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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if (MulOp0.getOpcode() == ISD::SIGN_EXTEND) {
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SDValue Sext0 = MulOp0.getOperand(0);
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if (Sext0.getNode()->getValueType(0) != MVT::i32) {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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OP0 = Sext0;
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@ -825,7 +835,8 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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if (LD->getMemoryVT() != MVT::i32 ||
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LD->getExtensionType() != ISD::SEXTLOAD ||
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LD->getAddressingMode() != ISD::UNINDEXED) {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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SDValue Chain = LD->getChain();
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@ -835,14 +846,16 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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LD->getBasePtr(), TargetConst0,
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Chain), 0);
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} else {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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// Same goes for the second operand.
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if (MulOp1.getOpcode() == ISD::SIGN_EXTEND) {
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SDValue Sext1 = MulOp1.getOperand(0);
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if (Sext1.getNode()->getValueType(0) != MVT::i32) {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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OP1 = Sext1;
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@ -851,7 +864,8 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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if (LD->getMemoryVT() != MVT::i32 ||
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LD->getExtensionType() != ISD::SEXTLOAD ||
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LD->getAddressingMode() != ISD::UNINDEXED) {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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SDValue Chain = LD->getChain();
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@ -861,20 +875,21 @@ SDNode *HexagonDAGToDAGISel::SelectMul(SDNode *N) {
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LD->getBasePtr(), TargetConst0,
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Chain), 0);
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} else {
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return SelectCode(N);
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SelectCode(N);
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return;
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}
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// Generate a mpy instruction.
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SDNode *Result = CurDAG->getMachineNode(Hexagon::M2_dpmpyss_s0, dl, MVT::i64,
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OP0, OP1);
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ReplaceUses(N, Result);
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return Result;
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ReplaceNode(N, Result);
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return;
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}
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return SelectCode(N);
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SelectCode(N);
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}
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SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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void HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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SDLoc dl(N);
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if (N->getValueType(0) == MVT::i32) {
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SDValue Shl_0 = N->getOperand(0);
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@ -898,8 +913,8 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl,
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MVT::i32, Mul_0, Val);
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ReplaceUses(N, Result);
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return Result;
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ReplaceNode(N, Result);
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return;
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}
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}
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@ -927,8 +942,8 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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SDNode* Result =
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CurDAG->getMachineNode(Hexagon::M2_mpysmi, dl, MVT::i32,
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Shl2_0, Val);
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ReplaceUses(N, Result);
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return Result;
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ReplaceNode(N, Result);
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return;
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}
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}
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}
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@ -937,7 +952,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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}
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}
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}
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return SelectCode(N);
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SelectCode(N);
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}
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@ -951,7 +966,7 @@ SDNode *HexagonDAGToDAGISel::SelectSHL(SDNode *N) {
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// compiler. Architecture defines them as 8-bit registers.
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// We want to preserve all the lower 8-bits and, not just 1 LSB bit.
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//
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SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
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void HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
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SDLoc dl(N);
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SDValue Op0 = N->getOperand(0);
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@ -977,11 +992,14 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
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SDValue(Mask,0), SDValue(OnesReg,0));
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SDValue SubR = CurDAG->getTargetConstant(Hexagon::subreg_loreg, dl,
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MVT::i32);
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return CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
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SDValue(And,0), SubR);
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ReplaceNode(N, CurDAG->getMachineNode(Hexagon::EXTRACT_SUBREG, dl, ExVT,
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SDValue(And, 0), SubR));
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return;
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}
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return CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
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SDValue(Mask,0), SDValue(OnesReg,0));
|
||||
ReplaceNode(N,
|
||||
CurDAG->getMachineNode(Hexagon::A2_andp, dl, ExVT,
|
||||
SDValue(Mask, 0), SDValue(OnesReg, 0)));
|
||||
return;
|
||||
}
|
||||
|
||||
SDNode *IsIntrinsic = N->getOperand(0).getNode();
|
||||
|
|
@ -1003,34 +1021,36 @@ SDNode *HexagonDAGToDAGISel::SelectZeroExtend(SDNode *N) {
|
|||
MVT::i64, MVT::Other,
|
||||
SDValue(Result_2, 0),
|
||||
SDValue(Result_1, 0));
|
||||
ReplaceUses(N, Result_3);
|
||||
return Result_3;
|
||||
ReplaceNode(N, Result_3);
|
||||
return;
|
||||
}
|
||||
if (N->getValueType(0) == MVT::i32) {
|
||||
// Convert the zero_extend to Rs = Pd
|
||||
SDNode* RsPd = CurDAG->getMachineNode(Hexagon::C2_tfrpr, dl,
|
||||
MVT::i32,
|
||||
SDValue(IsIntrinsic, 0));
|
||||
ReplaceUses(N, RsPd);
|
||||
return RsPd;
|
||||
ReplaceNode(N, RsPd);
|
||||
return;
|
||||
}
|
||||
llvm_unreachable("Unexpected value type");
|
||||
}
|
||||
}
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Handling intrinsics for circular load and bitreverse load.
|
||||
//
|
||||
SDNode *HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
|
||||
if (MachineSDNode *L = LoadInstrForLoadIntrinsic(N))
|
||||
return StoreInstrForLoadIntrinsic(L, N);
|
||||
return SelectCode(N);
|
||||
void HexagonDAGToDAGISel::SelectIntrinsicWChain(SDNode *N) {
|
||||
if (MachineSDNode *L = LoadInstrForLoadIntrinsic(N)) {
|
||||
StoreInstrForLoadIntrinsic(L, N);
|
||||
return;
|
||||
}
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
|
||||
unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
|
||||
unsigned Bits;
|
||||
switch (IID) {
|
||||
|
|
@ -1041,7 +1061,8 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
|
|||
Bits = 16;
|
||||
break;
|
||||
default:
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
|
||||
SDValue V = N->getOperand(1);
|
||||
|
|
@ -1050,34 +1071,41 @@ SDNode *HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
|
|||
SDValue R = CurDAG->getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
|
||||
N->getOperand(0), U);
|
||||
ReplaceNode(N, R.getNode());
|
||||
return SelectCode(R.getNode());
|
||||
SelectCode(R.getNode());
|
||||
return;
|
||||
}
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
//
|
||||
// Map floating point constant values.
|
||||
//
|
||||
SDNode *HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectConstantFP(SDNode *N) {
|
||||
SDLoc dl(N);
|
||||
ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
|
||||
APFloat APF = CN->getValueAPF();
|
||||
if (N->getValueType(0) == MVT::f32) {
|
||||
return CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
|
||||
CurDAG->getTargetConstantFP(APF.convertToFloat(), dl, MVT::f32));
|
||||
ReplaceNode(
|
||||
N, CurDAG->getMachineNode(Hexagon::TFRI_f, dl, MVT::f32,
|
||||
CurDAG->getTargetConstantFP(
|
||||
APF.convertToFloat(), dl, MVT::f32)));
|
||||
return;
|
||||
}
|
||||
else if (N->getValueType(0) == MVT::f64) {
|
||||
return CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
|
||||
CurDAG->getTargetConstantFP(APF.convertToDouble(), dl, MVT::f64));
|
||||
ReplaceNode(
|
||||
N, CurDAG->getMachineNode(Hexagon::CONST64_Float_Real, dl, MVT::f64,
|
||||
CurDAG->getTargetConstantFP(
|
||||
APF.convertToDouble(), dl, MVT::f64)));
|
||||
return;
|
||||
}
|
||||
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
//
|
||||
// Map predicate true (encoded as -1 in LLVM) to a XOR.
|
||||
//
|
||||
SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
|
||||
SDLoc dl(N);
|
||||
if (N->getValueType(0) == MVT::i1) {
|
||||
SDNode* Result = 0;
|
||||
|
|
@ -1088,28 +1116,30 @@ SDNode *HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
|
|||
Result = CurDAG->getMachineNode(Hexagon::TFR_PdFalse, dl, MVT::i1);
|
||||
}
|
||||
if (Result) {
|
||||
ReplaceUses(N, Result);
|
||||
return Result;
|
||||
ReplaceNode(N, Result);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
|
||||
//
|
||||
// Map add followed by a asr -> asr +=.
|
||||
//
|
||||
SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
|
||||
SDLoc dl(N);
|
||||
if (N->getValueType(0) != MVT::i32) {
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
// Identify nodes of the form: add(asr(...)).
|
||||
SDNode* Src1 = N->getOperand(0).getNode();
|
||||
if (Src1->getOpcode() != ISD::SRA || !Src1->hasOneUse()
|
||||
|| Src1->getValueType(0) != MVT::i32) {
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
|
||||
// Build Rd = Rd' + asr(Rs, Rt). The machine constraints will ensure that
|
||||
|
|
@ -1118,9 +1148,7 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
|
|||
N->getOperand(1),
|
||||
Src1->getOperand(0),
|
||||
Src1->getOperand(1));
|
||||
ReplaceUses(N, Result);
|
||||
|
||||
return Result;
|
||||
ReplaceNode(N, Result);
|
||||
}
|
||||
|
||||
//
|
||||
|
|
@ -1129,26 +1157,32 @@ SDNode *HexagonDAGToDAGISel::SelectAdd(SDNode *N) {
|
|||
// OR -> setbit
|
||||
// XOR/FNEG ->toggle_bit.
|
||||
//
|
||||
SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
||||
SDLoc dl(N);
|
||||
EVT ValueVT = N->getValueType(0);
|
||||
|
||||
// We handle only 32 and 64-bit bit ops.
|
||||
if (!(ValueVT == MVT::i32 || ValueVT == MVT::i64 ||
|
||||
ValueVT == MVT::f32 || ValueVT == MVT::f64))
|
||||
return SelectCode(N);
|
||||
ValueVT == MVT::f32 || ValueVT == MVT::f64)) {
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
|
||||
// We handly only fabs and fneg for V5.
|
||||
unsigned Opc = N->getOpcode();
|
||||
if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps())
|
||||
return SelectCode(N);
|
||||
if ((Opc == ISD::FABS || Opc == ISD::FNEG) && !HST->hasV5TOps()) {
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
|
||||
int64_t Val = 0;
|
||||
if (Opc != ISD::FABS && Opc != ISD::FNEG) {
|
||||
if (N->getOperand(1).getOpcode() == ISD::Constant)
|
||||
Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
|
||||
else
|
||||
return SelectCode(N);
|
||||
else {
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
if (Opc == ISD::AND) {
|
||||
|
|
@ -1156,8 +1190,10 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
|||
if ((ValueVT == MVT::i32 && isPowerOf2_32(~Val)) ||
|
||||
(ValueVT == MVT::i64 && isPowerOf2_64(~Val)))
|
||||
Val = ~Val;
|
||||
else
|
||||
return SelectCode(N);
|
||||
else {
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
// If OR or AND is being fed by shl, srl and, sra don't do this change,
|
||||
|
|
@ -1170,7 +1206,8 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
|||
case ISD::SRA:
|
||||
case ISD::SRL:
|
||||
case ISD::SHL:
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1178,8 +1215,10 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
|||
unsigned BitPos = 0;
|
||||
if (Opc != ISD::FABS && Opc != ISD::FNEG) {
|
||||
if ((ValueVT == MVT::i32 && !isPowerOf2_32(Val)) ||
|
||||
(ValueVT == MVT::i64 && !isPowerOf2_64(Val)))
|
||||
return SelectCode(N);
|
||||
(ValueVT == MVT::i64 && !isPowerOf2_64(Val))) {
|
||||
SelectCode(N);
|
||||
return;
|
||||
}
|
||||
|
||||
// Get the bit position.
|
||||
BitPos = countTrailingZeros(uint64_t(Val));
|
||||
|
|
@ -1256,12 +1295,11 @@ SDNode *HexagonDAGToDAGISel::SelectBitOp(SDNode *N) {
|
|||
}
|
||||
}
|
||||
|
||||
ReplaceUses(N, Result);
|
||||
return Result;
|
||||
ReplaceNode(N, Result);
|
||||
}
|
||||
|
||||
|
||||
SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
|
||||
MachineFrameInfo *MFI = MF->getFrameInfo();
|
||||
const HexagonFrameLowering *HFI = HST->getFrameLowering();
|
||||
int FX = cast<FrameIndexSDNode>(N)->getIndex();
|
||||
|
|
@ -1289,59 +1327,71 @@ SDNode *HexagonDAGToDAGISel::SelectFrameIndex(SDNode *N) {
|
|||
|
||||
if (N->getHasDebugValue())
|
||||
CurDAG->TransferDbgValues(SDValue(N, 0), SDValue(R, 0));
|
||||
return R;
|
||||
ReplaceNode(N, R);
|
||||
}
|
||||
|
||||
|
||||
SDNode *HexagonDAGToDAGISel::SelectImpl(SDNode *N) {
|
||||
void HexagonDAGToDAGISel::Select(SDNode *N) {
|
||||
if (N->isMachineOpcode()) {
|
||||
N->setNodeId(-1);
|
||||
return nullptr; // Already selected.
|
||||
return; // Already selected.
|
||||
}
|
||||
|
||||
switch (N->getOpcode()) {
|
||||
case ISD::Constant:
|
||||
return SelectConstant(N);
|
||||
SelectConstant(N);
|
||||
return;
|
||||
|
||||
case ISD::ConstantFP:
|
||||
return SelectConstantFP(N);
|
||||
SelectConstantFP(N);
|
||||
return;
|
||||
|
||||
case ISD::FrameIndex:
|
||||
return SelectFrameIndex(N);
|
||||
SelectFrameIndex(N);
|
||||
return;
|
||||
|
||||
case ISD::ADD:
|
||||
return SelectAdd(N);
|
||||
SelectAdd(N);
|
||||
return;
|
||||
|
||||
case ISD::SHL:
|
||||
return SelectSHL(N);
|
||||
SelectSHL(N);
|
||||
return;
|
||||
|
||||
case ISD::LOAD:
|
||||
return SelectLoad(N);
|
||||
SelectLoad(N);
|
||||
return;
|
||||
|
||||
case ISD::STORE:
|
||||
return SelectStore(N);
|
||||
SelectStore(N);
|
||||
return;
|
||||
|
||||
case ISD::MUL:
|
||||
return SelectMul(N);
|
||||
SelectMul(N);
|
||||
return;
|
||||
|
||||
case ISD::AND:
|
||||
case ISD::OR:
|
||||
case ISD::XOR:
|
||||
case ISD::FABS:
|
||||
case ISD::FNEG:
|
||||
return SelectBitOp(N);
|
||||
SelectBitOp(N);
|
||||
return;
|
||||
|
||||
case ISD::ZERO_EXTEND:
|
||||
return SelectZeroExtend(N);
|
||||
SelectZeroExtend(N);
|
||||
return;
|
||||
|
||||
case ISD::INTRINSIC_W_CHAIN:
|
||||
return SelectIntrinsicWChain(N);
|
||||
SelectIntrinsicWChain(N);
|
||||
return;
|
||||
|
||||
case ISD::INTRINSIC_WO_CHAIN:
|
||||
return SelectIntrinsicWOChain(N);
|
||||
SelectIntrinsicWOChain(N);
|
||||
return;
|
||||
}
|
||||
|
||||
return SelectCode(N);
|
||||
SelectCode(N);
|
||||
}
|
||||
|
||||
bool HexagonDAGToDAGISel::
|
||||
|
|
|
|||
Loading…
Reference in New Issue