forked from OSchip/llvm-project
[X86] Split SCALEF(S) ISD opcodes into a version without rounding mode.
llvm-svn: 355806
This commit is contained in:
Craig Topper
parent
a0b5338834
commit
ecbc141dbf
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@ -22111,34 +22111,22 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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return getScalarMaskingNode(DAG.getNode(Opc, dl, VT, Src1, Src2),
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Mask, passThru, Subtarget, DAG);
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}
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case INTR_TYPE_SCALAR_MASK_RM: {
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assert(Op.getNumOperands() == 6 && "Unexpected number of operands");
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue Src0 = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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SDValue Rnd = Op.getOperand(5);
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return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2,
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Rnd),
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Mask, Src0, Subtarget, DAG);
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}
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case INTR_TYPE_2OP_MASK_RM: {
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case INTR_TYPE_2OP_MASK: {
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SDValue Src1 = Op.getOperand(1);
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SDValue Src2 = Op.getOperand(2);
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SDValue PassThru = Op.getOperand(3);
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SDValue Mask = Op.getOperand(4);
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// We specify 2 possible modes for intrinsics, with/without rounding
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// modes.
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// First, we check if the intrinsic have rounding mode (6 operands),
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// if not, we set rounding mode to "current".
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SDValue Rnd;
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if (Op.getNumOperands() == 6)
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Rnd = Op.getOperand(5);
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else
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Rnd = DAG.getConstant(X86::STATIC_ROUNDING::CUR_DIRECTION, dl, MVT::i32);
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return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT,
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Src1, Src2, Rnd),
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Mask, PassThru, Subtarget, DAG);
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SDValue NewOp;
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if (IntrData->Opc1 != 0) {
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SDValue Rnd = Op.getOperand(5);
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if (isRoundModeSAEToX(Rnd))
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NewOp = DAG.getNode(IntrData->Opc1, dl, VT, Src1, Src2, Rnd);
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else if (!isRoundModeCurDirection(Rnd))
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return SDValue();
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}
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if (!NewOp)
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NewOp = DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2);
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return getVectorMaskingNode(NewOp, Mask, PassThru, Subtarget, DAG);
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}
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case INTR_TYPE_2OP_MASK_SAE: {
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SDValue Src1 = Op.getOperand(1);
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@ -27776,7 +27764,9 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FGETEXPS: return "X86ISD::FGETEXPS";
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case X86ISD::FGETEXPS_SAE: return "X86ISD::FGETEXPS_SAE";
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case X86ISD::SCALEF: return "X86ISD::SCALEF";
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case X86ISD::SCALEF_RND: return "X86ISD::SCALEF_RND";
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case X86ISD::SCALEFS: return "X86ISD::SCALEFS";
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case X86ISD::SCALEFS_RND: return "X86ISD::SCALEFS_RND";
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case X86ISD::AVG: return "X86ISD::AVG";
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case X86ISD::MULHRS: return "X86ISD::MULHRS";
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case X86ISD::SINT_TO_FP_RND: return "X86ISD::SINT_TO_FP_RND";
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@ -224,8 +224,8 @@ namespace llvm {
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// Extract Normalized Mantissas.
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VGETMANT, VGETMANT_SAE, VGETMANTS, VGETMANTS_SAE,
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// FP Scale.
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SCALEF,
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SCALEFS,
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SCALEF, SCALEF_RND,
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SCALEFS, SCALEFS_RND,
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// Unsigned Integer average.
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AVG,
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@ -5790,20 +5790,19 @@ multiclass avx512_fp_scalef_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
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defm rr: AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>,
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(_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
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EVEX_4V, Sched<[sched]>;
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defm rm: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2), (i32 FROUND_CURRENT))>,
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(OpNode _.RC:$src1, (_.LdFrag addr:$src2))>,
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EVEX_4V, Sched<[sched.Folded, sched.ReadAfterFold]>;
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defm rmb: AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"${src2}"##_.BroadcastStr##", $src1",
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"$src1, ${src2}"##_.BroadcastStr,
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(OpNode _.RC:$src1, (_.VT (X86VBroadcast
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(_.ScalarLdFrag addr:$src2))),
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(i32 FROUND_CURRENT))>,
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(_.ScalarLdFrag addr:$src2))))>,
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EVEX_4V, EVEX_B, Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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}
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@ -5814,46 +5813,46 @@ multiclass avx512_fp_scalef_scalar<bits<8> opc, string OpcodeStr, SDNode OpNode,
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defm rr: AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, (i32 FROUND_CURRENT)))>,
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(_.VT (OpNode _.RC:$src1, _.RC:$src2))>,
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Sched<[sched]>;
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defm rm: AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src1, _.IntScalarMemOp:$src2), OpcodeStr##_.Suffix,
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"$src2, $src1", "$src1, $src2",
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(OpNode _.RC:$src1, _.ScalarIntMemCPat:$src2,
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(i32 FROUND_CURRENT))>,
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(OpNode _.RC:$src1, _.ScalarIntMemCPat:$src2)>,
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Sched<[sched.Folded, sched.ReadAfterFold]>;
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}
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}
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multiclass avx512_fp_scalef_all<bits<8> opc, bits<8> opcScaler, string OpcodeStr,
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SDNode OpNode, SDNode OpNodeScal,
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X86SchedWriteWidths sched> {
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defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.ZMM, v16f32_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, sched.ZMM, v16f32_info>,
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defm PSZ : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.ZMM, v16f32_info>,
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avx512_fp_round_packed<opc, OpcodeStr, X86scalefRnd, sched.ZMM, v16f32_info>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.ZMM, v8f64_info>,
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avx512_fp_round_packed<opc, OpcodeStr, OpNode, sched.ZMM, v8f64_info>,
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defm PDZ : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.ZMM, v8f64_info>,
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avx512_fp_round_packed<opc, OpcodeStr, X86scalefRnd, sched.ZMM, v8f64_info>,
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EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
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defm SSZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f32x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info, OpNodeScal, sched.Scl>,
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EVEX_4V,EVEX_CD8<32, CD8VT1>;
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defm SDZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, OpNodeScal, sched.Scl, f64x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info, OpNodeScal, sched.Scl>,
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EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
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defm SSZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, X86scalefs, sched.Scl, f32x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"ss", f32x_info,
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X86scalefsRnd, sched.Scl>,
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EVEX_4V,EVEX_CD8<32, CD8VT1>;
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defm SDZ : avx512_fp_scalef_scalar<opcScaler, OpcodeStr, X86scalefs, sched.Scl, f64x_info>,
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avx512_fp_scalar_round<opcScaler, OpcodeStr##"sd", f64x_info,
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X86scalefsRnd, sched.Scl>,
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EVEX_4V, EVEX_CD8<64, CD8VT1>, VEX_W;
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// Define only if AVX512VL feature is present.
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let Predicates = [HasVLX] in {
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defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.XMM, v4f32x_info>,
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defm PSZ128 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.XMM, v4f32x_info>,
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EVEX_V128, EVEX_CD8<32, CD8VF>;
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defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.YMM, v8f32x_info>,
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defm PSZ256 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.YMM, v8f32x_info>,
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EVEX_V256, EVEX_CD8<32, CD8VF>;
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defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.XMM, v2f64x_info>,
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defm PDZ128 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.XMM, v2f64x_info>,
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EVEX_V128, VEX_W, EVEX_CD8<64, CD8VF>;
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defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, OpNode, sched.YMM, v4f64x_info>,
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defm PDZ256 : avx512_fp_scalef_p<opc, OpcodeStr, X86scalef, sched.YMM, v4f64x_info>,
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EVEX_V256, VEX_W, EVEX_CD8<64, CD8VF>;
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}
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}
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defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef", X86scalef, X86scalefs,
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defm VSCALEF : avx512_fp_scalef_all<0x2C, 0x2D, "vscalef",
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SchedWriteFAdd>, T8PD, NotEVEX2VEXConvertible;
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//===----------------------------------------------------------------------===//
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@ -465,8 +465,10 @@ def X86fmaxSAE : SDNode<"X86ISD::FMAX_SAE", SDTFPBinOp>;
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def X86fmaxSAEs : SDNode<"X86ISD::FMAXS_SAE", SDTFPBinOp>;
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def X86fminSAE : SDNode<"X86ISD::FMIN_SAE", SDTFPBinOp>;
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def X86fminSAEs : SDNode<"X86ISD::FMINS_SAE", SDTFPBinOp>;
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def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOpRound>;
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def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOpRound>;
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def X86scalef : SDNode<"X86ISD::SCALEF", SDTFPBinOp>;
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def X86scalefRnd : SDNode<"X86ISD::SCALEF_RND", SDTFPBinOpRound>;
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def X86scalefs : SDNode<"X86ISD::SCALEFS", SDTFPBinOp>;
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def X86scalefsRnd: SDNode<"X86ISD::SCALEFS_RND", SDTFPBinOpRound>;
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def X86fsqrtRnd : SDNode<"X86ISD::FSQRT_RND", SDTFPUnaryOpRound>;
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def X86fsqrts : SDNode<"X86ISD::FSQRTS", SDTFPBinOp>;
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def X86fsqrtRnds : SDNode<"X86ISD::FSQRTS_RND", SDTFPBinOpRound>;
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@ -26,11 +26,10 @@ enum IntrinsicType : uint16_t {
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CVTPD2PS_MASK,
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INTR_TYPE_1OP_SAE, INTR_TYPE_2OP_SAE,
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INTR_TYPE_1OP_MASK_SAE, INTR_TYPE_2OP_MASK_SAE, INTR_TYPE_3OP_MASK_SAE,
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INTR_TYPE_1OP_MASK,
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INTR_TYPE_2OP_MASK_RM,
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INTR_TYPE_1OP_MASK, INTR_TYPE_2OP_MASK,
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IFMA_OP, VPERM_2OP, INTR_TYPE_SCALAR_MASK, INTR_TYPE_SCALAR_MASK_SAE,
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INTR_TYPE_SCALAR_MASK_RND,
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INTR_TYPE_SCALAR_MASK_RM, INTR_TYPE_3OP_SCALAR_MASK_SAE,
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INTR_TYPE_3OP_SCALAR_MASK_SAE,
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COMPRESS_EXPAND_IN_REG,
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TRUNCATE_TO_REG, CVTPS2PH_MASK, CVTPD2DQ_MASK, CVTQQ2PS_MASK,
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TRUNCATE_TO_MEM_VI8, TRUNCATE_TO_MEM_VI16, TRUNCATE_TO_MEM_VI32,
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@ -756,22 +755,22 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
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X86ISD::VRNDSCALES, X86ISD::VRNDSCALES_SAE),
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X86_INTRINSIC_DATA(avx512_mask_rndscale_ss, INTR_TYPE_SCALAR_MASK,
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X86ISD::VRNDSCALES, X86ISD::VRNDSCALES_SAE),
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_128, INTR_TYPE_2OP_MASK_RM,
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_128, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_256, INTR_TYPE_2OP_MASK_RM,
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_256, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_512, INTR_TYPE_2OP_MASK_RM,
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X86_INTRINSIC_DATA(avx512_mask_scalef_pd_512, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, X86ISD::SCALEF_RND),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_128, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_128, INTR_TYPE_2OP_MASK_RM,
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_256, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_256, INTR_TYPE_2OP_MASK_RM,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_512, INTR_TYPE_2OP_MASK_RM,
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X86ISD::SCALEF, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_sd, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::SCALEFS, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ss, INTR_TYPE_SCALAR_MASK_RM,
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X86ISD::SCALEFS, 0),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ps_512, INTR_TYPE_2OP_MASK,
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X86ISD::SCALEF, X86ISD::SCALEF_RND),
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X86_INTRINSIC_DATA(avx512_mask_scalef_sd, INTR_TYPE_SCALAR_MASK,
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X86ISD::SCALEFS, X86ISD::SCALEFS_RND),
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X86_INTRINSIC_DATA(avx512_mask_scalef_ss, INTR_TYPE_SCALAR_MASK,
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X86ISD::SCALEFS, X86ISD::SCALEFS_RND),
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X86_INTRINSIC_DATA(avx512_mask_sqrt_sd, INTR_TYPE_SCALAR_MASK,
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X86ISD::FSQRTS, X86ISD::FSQRTS_RND),
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X86_INTRINSIC_DATA(avx512_mask_sqrt_ss, INTR_TYPE_SCALAR_MASK,
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