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ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns. 

The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

llvm-svn: 147170
This commit is contained in:
Jim Grosbach 2011-12-22 19:55:21 +00:00
parent b65dd04923
commit f0d25117c6
1 changed files with 3 additions and 0 deletions
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3
llvm/lib/Target/ARM/ARMInstrFormats.td
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@ -1594,8 +1594,11 @@ class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
dag oops, dag iops, InstrItinClass itin, string opc, string asm, dag oops, dag iops, InstrItinClass itin, string opc, string asm,
list<dag> pattern> list<dag> pattern>
: AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> { : AVConv1I<op1, op2, op3, op4, oops, iops, itin, opc, asm, pattern> {
bits<5> fbits;
// size (fixed-point number): sx == 0 ? 16 : 32 // size (fixed-point number): sx == 0 ? 16 : 32
let Inst{7} = op5; // sx let Inst{7} = op5; // sx
let Inst{5} = fbits{0};
let Inst{3-0} = fbits{4-1};
} }
// VFP conversion instructions, if no NEON // VFP conversion instructions, if no NEON