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optimize fxor like for 

llvm-svn: 46345
This commit is contained in:
Chris Lattner 2008-01-25 06:14:17 +00:00
parent 84ab724e06
commit f4523c35cb
1 changed files with 6 additions and 3 deletions
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9
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -5627,10 +5627,12 @@ static SDOperand PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
return SDOperand(); return SDOperand();
} }
/// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR nodes. /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and
/// X86ISD::FXOR nodes.
static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) { static SDOperand PerformFORCombine(SDNode *N, SelectionDAG &DAG) {
// FOR(0.0, x) -> x assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR);
// FOR(x, 0.0) -> x // F[X]OR(0.0, x) -> x
// F[X]OR(x, 0.0) -> x
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
if (C->getValueAPF().isPosZero()) if (C->getValueAPF().isPosZero())
return N->getOperand(1); return N->getOperand(1);
@ -5661,6 +5663,7 @@ SDOperand X86TargetLowering::PerformDAGCombine(SDNode *N,
default: break; default: break;
case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget); case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, Subtarget);
case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget);
case X86ISD::FXOR:
case X86ISD::FOR: return PerformFORCombine(N, DAG); case X86ISD::FOR: return PerformFORCombine(N, DAG);
case X86ISD::FAND: return PerformFANDCombine(N, DAG); case X86ISD::FAND: return PerformFANDCombine(N, DAG);
} }