forked from OSchip/llvm-project
parent
0b8bc00424
commit
f93b3f46f8
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@ -219,11 +219,16 @@ def : Pat<(i64 immZExt16:$in),
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def : Pat<(i64 imm:$imm),
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(ORi64 (LUi64 (HI16 imm:$imm)), (LO16 imm:$imm))>;
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// zextloadi32_u
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def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>,
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Requires<[IsN64]>;
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def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>,
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Requires<[NotN64]>;
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// extended loads
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let Predicates = [NotN64] in {
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def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64 addr:$a), 0), 0)>;
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def : Pat<(zextloadi32_u addr:$a), (DSRL32 (DSLL32 (ULW64 addr:$a), 0), 0)>;
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}
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let Predicates = [IsN64] in {
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def : Pat<(extloadi32_a addr:$a), (DSRL32 (DSLL32 (LW64_P8 addr:$a), 0), 0)>;
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def : Pat<(zextloadi32_u addr:$a),
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(DSRL32 (DSLL32 (ULW64_P8 addr:$a), 0), 0)>;
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}
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// hi/lo relocs
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def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
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