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Remove the "Register &reg" parameter from the BXWritePC(), LoadWritePC(), and ALUWritePC() 

methods of EmulateInstructionARM class.  The context data structure should provide sufficient
information already.

llvm-svn: 125596
This commit is contained in:
Johnny Chen 2011-02-15 21:08:58 +00:00
parent 4e0f4957bc
commit f976896b83
3 changed files with 31 additions and 46 deletions
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17
lldb/include/lldb/Core/EmulateInstruction.h
View File

@ -176,7 +176,7 @@ public:
eInfoTypeAddress, eInfoTypeAddress,
eInfoTypeModeAndImmediate, eInfoTypeModeAndImmediate,
eInfoTypeModeAndImmediateSigned, eInfoTypeModeAndImmediateSigned,
eInfoTypeModeAndRegister, eInfoTypeMode,
eInfoTypeNoArgs eInfoTypeNoArgs
} InfoType; } InfoType;
@ -232,7 +232,7 @@ public:
struct ModeAndImmediate struct ModeAndImmediate
{ {
uint32_t mode; // eModeARM or eModeThumb uint32_t mode; // eModeARM or eModeThumb
uint32_t data_value; //immdiate data uint32_t data_value; // immdiate data
} ModeAndImmediate; } ModeAndImmediate;
struct ModeAndImmediateSigned struct ModeAndImmediateSigned
@ -241,11 +241,7 @@ public:
int32_t signed_data_value; // signed immdiate data int32_t signed_data_value; // signed immdiate data
} ModeAndImmediateSigned; } ModeAndImmediateSigned;
struct ModeAndRegister uint32_t mode; // eModeARM or eModeThumb
{
uint32_t mode; // eModeARM or eModeThumb
Register reg;
} ModeAndRegister;
} info; } info;
@ -329,11 +325,10 @@ public:
} }
void void
SetModeAndRegister (uint32_t mode, Register reg) SetMode (uint32_t mode)
{ {
info_type = eInfoTypeModeAndRegister; info_type = eInfoTypeMode;
info.ModeAndRegister.mode = mode; info.mode = mode;
info.ModeAndRegister.reg = reg;
} }
void void

54
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
View File

@ -427,7 +427,7 @@ EmulateInstructionARM::EmulatePop (ARMEncoding encoding)
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, dwarf_reg)) if (!LoadWritePC(context, data))
return false; return false;
addr += addr_byte_size; addr += addr_byte_size;
} }
@ -628,7 +628,7 @@ EmulateInstructionARM::EmulateMovRdRm (ARMEncoding encoding)
if (Rd == 15) if (Rd == 15)
{ {
if (!ALUWritePC (context, reg_value, dwarf_reg)) if (!ALUWritePC (context, reg_value))
return false; return false;
} }
else else
@ -711,12 +711,9 @@ EmulateInstructionARM::EmulateMovRdImm (ARMEncoding encoding)
context.type = EmulateInstruction::eContextImmediate; context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs (); context.SetNoArgs ();
Register dummy_reg;
dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
if (Rd == 15) if (Rd == 15)
{ {
if (!ALUWritePC (context, result, dummy_reg)) if (!ALUWritePC (context, result))
return false; return false;
} }
else else
@ -801,8 +798,7 @@ EmulateInstructionARM::EmulateMvnRdImm (ARMEncoding encoding)
if (Rd == 15) if (Rd == 15)
{ {
Register dummy_reg; if (!ALUWritePC (context, result))
if (!ALUWritePC (context, result, dummy_reg))
return false; return false;
} }
else else
@ -909,7 +905,7 @@ EmulateInstructionARM::EmulateLDRRtPCRelative (ARMEncoding encoding)
if (Bits32(address, 1, 0) == 0) if (Bits32(address, 1, 0) == 0)
{ {
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, pc_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
else else
@ -1205,7 +1201,7 @@ EmulateInstructionARM::EmulateBLXRm (ARMEncoding encoding)
context.SetRegister (dwarf_reg); context.SetRegister (dwarf_reg);
if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr)) if (!WriteRegisterUnsigned (context, eRegisterKindGeneric, LLDB_REGNUM_GENERIC_RA, lr))
return false; return false;
if (!BXWritePC(context, target, dwarf_reg)) if (!BXWritePC(context, target))
return false; return false;
} }
return true; return true;
@ -1253,7 +1249,8 @@ EmulateInstructionARM::EmulateBXRm (ARMEncoding encoding)
Register dwarf_reg; Register dwarf_reg;
dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm); dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + Rm);
if (!BXWritePC(context, target, dwarf_reg)) context.SetRegister (dwarf_reg);
if (!BXWritePC(context, target))
return false; return false;
} }
return true; return true;
@ -1964,12 +1961,10 @@ EmulateInstructionARM::EmulateAddRdnRm (ARMEncoding encoding)
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextImmediate; context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs (); context.SetNoArgs ();
Register dummy_reg;
dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
if (Rd == 15) if (Rd == 15)
{ {
if (!ALUWritePC (context, result, dummy_reg)) if (!ALUWritePC (context, result))
return false; return false;
} }
else else
@ -2180,13 +2175,10 @@ EmulateInstructionARM::EmulateASRImm (ARMEncoding encoding)
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextImmediate; context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs (); context.SetNoArgs ();
Register dummy_reg;
dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
if (Rd == 15) if (Rd == 15)
{ {
if (!ALUWritePC (context, result, dummy_reg)) if (!ALUWritePC (context, result))
return false; return false;
} }
else else
@ -2333,7 +2325,7 @@ EmulateInstructionARM::EmulateLDM (ARMEncoding encoding)
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, dwarf_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
@ -2449,7 +2441,7 @@ EmulateInstructionARM::EmulateLDMDA (ARMEncoding encoding)
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, dwarf_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
@ -2590,7 +2582,7 @@ EmulateInstructionARM::EmulateLDMDB (ARMEncoding encoding)
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, dwarf_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
@ -2707,7 +2699,7 @@ EmulateInstructionARM::EmulateLDMIB (ARMEncoding encoding)
if (!success) if (!success)
return false; return false;
// In ARMv5T and above, this is an interworking branch. // In ARMv5T and above, this is an interworking branch.
if (!LoadWritePC(context, data, dwarf_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
@ -2809,8 +2801,6 @@ EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding)
EmulateInstruction::Context context; EmulateInstruction::Context context;
context.type = EmulateInstruction::eContextImmediate; context.type = EmulateInstruction::eContextImmediate;
context.SetNoArgs (); context.SetNoArgs ();
Register dummy_reg;
dummy_reg.SetRegister (eRegisterKindDWARF, dwarf_r0);
// Read memory from the address. // Read memory from the address.
data = ReadMemoryUnsigned(context, address, 4, 0, &success); data = ReadMemoryUnsigned(context, address, 4, 0, &success);
@ -2821,7 +2811,7 @@ EmulateInstructionARM::EmulateLDRRtRnImm (ARMEncoding encoding)
{ {
if (Bits32(address, 1, 0) == 0) if (Bits32(address, 1, 0) == 0)
{ {
if (!LoadWritePC(context, data, dummy_reg)) if (!LoadWritePC(context, data))
return false; return false;
} }
else else
@ -3831,7 +3821,7 @@ EmulateInstructionARM::BranchWritePC (const Context &context, uint32_t addr)
// As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr. // As a side effect, BXWritePC sets context.arg2 to eModeARM or eModeThumb by inspecting addr.
bool bool
EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register &reg) EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr)
{ {
addr_t target; addr_t target;
// If the CPSR is changed due to switching between ARM and Thumb ISETSTATE, // If the CPSR is changed due to switching between ARM and Thumb ISETSTATE,
@ -3847,7 +3837,7 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register &reg
cpsr_changed = true; cpsr_changed = true;
} }
target = addr & 0xfffffffe; target = addr & 0xfffffffe;
context.SetModeAndRegister (eModeThumb, reg); context.SetMode (eModeThumb);
} }
else if (BitIsClear(addr, 1)) else if (BitIsClear(addr, 1))
{ {
@ -3857,7 +3847,7 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register &reg
cpsr_changed = true; cpsr_changed = true;
} }
target = addr & 0xfffffffc; target = addr & 0xfffffffc;
context.SetModeAndRegister (eModeARM, reg); context.SetMode (eModeARM);
} }
else else
return false; // address<1:0> == '10' => UNPREDICTABLE return false; // address<1:0> == '10' => UNPREDICTABLE
@ -3875,20 +3865,20 @@ EmulateInstructionARM::BXWritePC (Context &context, uint32_t addr, Register &reg
// Dispatches to either BXWritePC or BranchWritePC based on architecture versions. // Dispatches to either BXWritePC or BranchWritePC based on architecture versions.
bool bool
EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr, Register &reg) EmulateInstructionARM::LoadWritePC (Context &context, uint32_t addr)
{ {
if (ArchVersion() >= ARMv5T) if (ArchVersion() >= ARMv5T)
return BXWritePC(context, addr, reg); return BXWritePC(context, addr);
else else
return BranchWritePC((const Context)context, addr); return BranchWritePC((const Context)context, addr);
} }
// Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set. // Dispatches to either BXWritePC or BranchWritePC based on architecture versions and current instruction set.
bool bool
EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr, Register &reg) EmulateInstructionARM::ALUWritePC (Context &context, uint32_t addr)
{ {
if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM) if (ArchVersion() >= ARMv7 && CurrentInstrSet() == eModeARM)
return BXWritePC(context, addr, reg); return BXWritePC(context, addr);
else else
return BranchWritePC((const Context)context, addr); return BranchWritePC((const Context)context, addr);
} }

6
lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h
View File

@ -158,13 +158,13 @@ public:
BranchWritePC(const Context &context, uint32_t addr); BranchWritePC(const Context &context, uint32_t addr);
bool bool
BXWritePC(Context &context, uint32_t addr, Register &reg); BXWritePC(Context &context, uint32_t addr);
bool bool
LoadWritePC(Context &context, uint32_t addr, Register &reg); LoadWritePC(Context &context, uint32_t addr);
bool bool
ALUWritePC(Context &context, uint32_t addr, Register &reg); ALUWritePC(Context &context, uint32_t addr);
Mode Mode
CurrentInstrSet(); CurrentInstrSet();