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10 Commits

Author SHA1 Message Date
Craig Topper a2137d6e09 [X86] Add -flax-vector-conversions=none to all of the x86 vector intrinsic header tests. 2020-01-23 20:43:50 -08:00
Craig Topper 07b6d3de1b [X86] Add new variadic avx512 compress/expand intrinsics that use vXi1 types for the mask argument. 
Custom lower the builtins to these intrinsics. This enables the middle end to optimize out bitcasts for the masks.

llvm-svn: 352344
 2019-01-28 07:03:10 +00:00
Craig Topper cd9e232a4d Recommit r350555 "[X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd builtins." 
The MSVC limit hit in AutoUpgrade.cpp has been worked around for now.

llvm-svn: 350568
 2019-01-07 21:00:41 +00:00
Craig Topper 33c9088783 Revert r350555 "[X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd builtins." 
Had to revert the LLVM patch this depends on to fix a MSVC compiler limit in AutoUpgrade.cpp

llvm-svn: 350563
 2019-01-07 19:39:25 +00:00
Craig Topper e34f2bb807 [X86] Use funnel shift intrinsics for the VBMI2 vshld/vshrd builtins. 
Differential Revision: https://reviews.llvm.org/D56365

llvm-svn: 350555
 2019-01-07 19:10:22 +00:00
Craig Topper b4f7c5f0fd [X86] Update VBMI2 vshld/vshrd tests to use an immediate that doesn't require a modulo. 
Planning to replace these with funnel shift intrinsics which would mask out the extra bits. This will help minimize test diffs.

llvm-svn: 350506
 2019-01-07 06:01:58 +00:00
Craig Topper 2527c378c6 [X86] Remove masking from avx512vbmi2 concat and shift by immediate builtins. Use select builtins instead. 
llvm-svn: 334577
 2018-06-13 07:19:28 +00:00
Craig Topper 3cce6a7ed9 [X86] Use target independent masked expandload and compressstore intrinsics to implement expandload/compressstore builtins. 
Summary: We've had these target independent intrinsics for at least a year and a half. Looks like they do exactly what we need here and the backend already supports them.

Reviewers: RKSimon, delena, spatel, GBuella

Reviewed By: RKSimon

Subscribers: cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D47693

llvm-svn: 334366
 2018-06-10 17:27:05 +00:00
Craig Topper 3d9305f28b [X86] Fix the names of a bunch of icelake intrinsics. 
Mostly this fixes the names of all the 128-bit intrinsics to start with _mm_ instead of _mm128_ as is the convention and what the Intel docs say.

This also fixes the name of the bitshuffle intrinsics to say epi64 for 128 and 256 bit versions.

llvm-svn: 333497
 2018-05-30 03:38:15 +00:00
Coby Tayree a09663a5c1 [x86][icelake][vbmi2] 
added vbmi2 feature recognition
added intrinsics support for vbmi2 instructions
_mm[128,256,512]_mask[z]_compress_epi[16,32]
_mm[128,256,512]_mask_compressstoreu_epi[16,32]
_mm[128,256,512]_mask[z]_expand_epi[16,32]
_mm[128,256,512]_mask[z]_expandloadu_epi[16,32]
_mm[128,256,512]_mask[z]_sh[l,r]di_epi[16,32,64]
_mm[128,256,512]_mask_sh[l,r]dv_epi[16,32,64]
matching a similar work on the backend (D40206)
Differential Revision: https://reviews.llvm.org/D41557

llvm-svn: 321487
 2017-12-27 11:25:07 +00:00