10 Commits

Author	SHA1	Message	Date
Craig Topper	a2137d6e09	[X86] Add -flax-vector-conversions=none to all of the x86 vector intrinsic header tests.	2020-01-23 20:43:50 -08:00
Craig Topper	f9cb127ca9	[X86] Add guards to some of the x86 intrinsic tests to skip 64-bit mode only intrinsics when compiled for 32-bit mode. ... All the command lines are for 64-bit mode, but sometimes I compile the tests in 32-bit mode to see what assembly we get and we need to skip these to do that. llvm-svn: 365668	2019-07-10 17:11:23 +00:00
Gabor Buella	5219ed89be	[X86] NFC Include immintrin.h in CodeGen tests ... Following r333110: "Move all Intel defined intrinsic includes into immintrin.h" llvm-svn: 333160	2018-05-24 07:09:08 +00:00
Elad Cohen	b107a22afb	[X86] Remove the mm_malloc.h include guard hack from the X86 builtins tests ... The X86 clang/test/CodeGen/*builtins.c tests define the mm_malloc.h include guard as a hack for avoiding its inclusion (mm_malloc.h requires a hosted environment since it expects stdlib.h to be available - which is not the case in these internal clang codegen tests). This patch removes this hack and instead passes -ffreestanding to clang cc1. Differential Revision: https://reviews.llvm.org/D24825 llvm-svn: 282581	2016-09-28 11:59:09 +00:00
Eric Christopher	abb2b54ad3	After PR28761 use -Wall with -Werror in builtins tests to identify ... possible problems in headers. llvm-svn: 277696	2016-08-04 06:02:50 +00:00
Simon Pilgrim	519c78f3ae	[X86][SSE42] Sync with llvm/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll ... llvm-svn: 269931	2016-05-18 14:29:55 +00:00
Simon Pilgrim	068c2ce836	[X86] Stripped backend codegen tests ... As discussed on the ml, backend tests need to be put in llvm/test/CodeGen/X86 as fast-isel tests using IR that is as close to what is generated here as possible. The llvm tests will (re)added in a future commit I will update PR24580 on this new plan llvm-svn: 254594	2015-12-03 08:45:21 +00:00
Eric Christopher	cd875efa78	Canonicalize some of the x86 builtin tests and either remove or comment ... about optimization options. llvm-svn: 250271	2015-10-14 05:40:21 +00:00
Chandler Carruth	cbe6411401	Fix the SSE4 byte sign extension in a cleaner way, and more thoroughly ... test that our intrinsics behave the same under -fsigned-char and -funsigned-char. This further testing uncovered that AVX-2 has a broken cmpgt for 8-bit elements, and has for a long time. This is fixed in the same way as SSE4 handles the case. The other ISA extensions currently work correctly because they use specific instruction intrinsics. As soon as they are rewritten in terms of generic IR, they will need to add these special casts. I've added the necessary testing to catch this however, so we shouldn't have to chase it down again. I considered changing the core typedef to be signed, but that seems like a bad idea. Notably, it would be an ABI break if anyone is reaching into the innards of the intrinsic headers and passing __v16qi on an API boundary. I can't be completely confident that this wouldn't happen due to a macro expanding in a lambda, etc., so it seems much better to leave it alone. It also matches GCC's behavior exactly. A fun side note is that for both GCC and Clang, -funsigned-char really does change the semantics of __v16qi. To observe this, consider: % cat x.cc #include <smmintrin.h> #include <iostream> int main() { __v16qi a = { 1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; __v16qi b = _mm_set1_epi8(-1); std::cout << (int)(a / b)[0] << ", " << (int)(a / b)[1] << '\n'; } % clang++ -o x x.cc && ./x -1, 1 % clang++ -funsigned-char -o x x.cc && ./x 0, 1 However, while this may be surprising, both Clang and GCC agree. Differential Revision: http://reviews.llvm.org/D13324 llvm-svn: 249097	2015-10-01 23:40:12 +00:00
Simon Pilgrim	de06f31885	[X86]][SSE42] Added SSE42 IR + assembly codegen builtin tests ... llvm-svn: 246944	2015-09-06 14:05:33 +00:00