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127 Commits

Author SHA1 Message Date
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Jim Grosbach 055de2c789 Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Jim Grosbach 5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Eric Christopher c9616f26bd Move rejection of NEON parameters earlier in fast isel call processing, 
note that we can actually handle some f64 arguments.

llvm-svn: 117209
 2010-10-23 09:37:17 +00:00
Evan Cheng 21abfc9450 Silence compiler warnings. 
llvm-svn: 117128
 2010-10-22 18:57:05 +00:00
Eric Christopher 93bbe6599f Add some basic ret instruction support to arm fast-isel. 
llvm-svn: 117085
 2010-10-22 01:28:00 +00:00
Eric Christopher 2f8637d393 These don't need to be virtual. 
llvm-svn: 117068
 2010-10-21 21:47:51 +00:00
Eric Christopher b353e4f579 Handle storing args to the stack for calls. 
llvm-svn: 117055
 2010-10-21 20:09:54 +00:00
Eric Christopher 73bc5b0f86 More load/store refactoring, call reg+offset simplification from within 
the emitter to handle the addresses. Only simplify the offset if we need
to - also fix bug where in addrmode 5 we weren't dividing the offset by
4, which showed up due to not always lowering.

llvm-svn: 117051
 2010-10-21 19:40:30 +00:00
Eric Christopher 4ac3ed0219 Custom lower f64 args passed in integer registers. 
llvm-svn: 116977
 2010-10-21 00:01:47 +00:00
Eric Christopher af719ef86b Fix a TODO by removing some unnecesary copies. 
llvm-svn: 116915
 2010-10-20 08:02:24 +00:00
Eric Christopher 7b92c2a9a0 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Eric Christopher 167a700229 Remove the check for invalid calling conventions. Testing shows that they're 
working just fine.

llvm-svn: 116698
 2010-10-18 06:49:12 +00:00
Eric Christopher c103c668ce Lift arg promotion from the X86 backend. This should be unified at some point. 
llvm-svn: 116694
 2010-10-18 02:17:53 +00:00
Eric Christopher a8a9f3c52b Now that we handle all allocas via a non-SP reg offset remove all of the 
special case handling for ARM::SP.

llvm-svn: 116688
 2010-10-17 11:08:44 +00:00
Eric Christopher 730764da62 Allow more load types to be materialized through the allocas. 
llvm-svn: 116683
 2010-10-17 06:07:26 +00:00
Eric Christopher d265b3fcfe Optimize GEP off of intermediate allocas. 
llvm-svn: 116681
 2010-10-17 01:51:42 +00:00
Eric Christopher a0b9c2e9c0 Fix comment. 
llvm-svn: 116680
 2010-10-17 01:42:53 +00:00
Eric Christopher abc3a9d34b Turn on AddOperator folding in GEP. 
llvm-svn: 116679
 2010-10-17 01:41:46 +00:00
Eric Christopher 947e422c46 Use the i12 immediate versions of the load instructions - they're handled 
more in the post-passes.

llvm-svn: 116678
 2010-10-17 01:40:27 +00:00
Eric Christopher c918d550b6 Fix some funky formatting that got through. 
llvm-svn: 116653
 2010-10-16 01:10:35 +00:00
Eric Christopher f410acbbd5 Make sure offset is 0 for load/store register to the stack call. 
llvm-svn: 116640
 2010-10-15 23:07:10 +00:00
Eric Christopher a3e64c1791 Fix else if -> if in store machinery. 
llvm-svn: 116628
 2010-10-15 22:32:37 +00:00
Eric Christopher a9b3901b47 Refactor ARM fast-isel reg + offset to be a base + offset. 
llvm-svn: 116622
 2010-10-15 21:32:12 +00:00
Eric Christopher e4b3d6b379 Expand GEP handling for constant offsets. 
llvm-svn: 116594
 2010-10-15 18:02:07 +00:00
Eric Christopher 21d0c173f4 Handle more complex GEP based loads and add a few TODOs to deal with 
GEP + alloca.

llvm-svn: 116474
 2010-10-14 09:29:41 +00:00
Jim Grosbach 340cd5174b A few 80 column fixes. 
llvm-svn: 116451
 2010-10-13 23:34:31 +00:00
Eric Christopher ef83e21b57 Update comment. 
llvm-svn: 116438
 2010-10-13 21:41:51 +00:00
Eric Christopher dd0821e7ff Start handling more global variables. 
llvm-svn: 116401
 2010-10-13 09:11:46 +00:00
Eric Christopher 22e051eef0 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Eric Christopher 7cd5cda6bb Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher db3bcc9910 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Eric Christopher d42340ecfd Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Eric Christopher 72b91c1765 We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Eric Christopher 71ef1af66b Make sure that the call stack adjustments have default operands. Also 
leave custom lowerings for later.

Fixes some nightly tests.

llvm-svn: 116232
 2010-10-11 21:20:02 +00:00
Eric Christopher e2a0b6841a Found a bug turning this on by default. Disable again for now. 
llvm-svn: 116220
 2010-10-11 20:26:21 +00:00
Eric Christopher 46cc854e5e Fix help text. 
llvm-svn: 116218
 2010-10-11 20:15:02 +00:00
Eric Christopher 5501b7e805 Change flag from Enable to Disable since we're enabled by default. 
Also don't use fast-isel on non-darwin since it's untested.

llvm-svn: 116217
 2010-10-11 20:05:22 +00:00
Eric Christopher 2276e87a65 Turn on arm fast isel by default. 
llvm-svn: 116212
 2010-10-11 18:48:18 +00:00
Eric Christopher e1bcb43bb9 Copy and pasteo. 
llvm-svn: 116198
 2010-10-11 08:40:05 +00:00
Eric Christopher 7ac602bc8e Whitespace cleanup in ARM fast isel. 
llvm-svn: 116197
 2010-10-11 08:38:55 +00:00
Eric Christopher eae1b38550 Add srem libcall support to ARM fast isel. 
llvm-svn: 116196
 2010-10-11 08:37:26 +00:00
Eric Christopher e11017c19e Add i8 sdiv support for ARM fast isel. 
llvm-svn: 116195
 2010-10-11 08:31:54 +00:00
Eric Christopher 511aa31965 Implement select handling for ARM fast-isel. 
llvm-svn: 116194
 2010-10-11 08:27:59 +00:00
Eric Christopher 548587c31c Fix the store part of this as well. Fixes smg2000. 
llvm-svn: 116123
 2010-10-08 23:52:16 +00:00
Eric Christopher 15bc2438d9 Move to thumb2 loads, fixes a problem with incoming registers 
as thumb1.

Fixes lencod.

llvm-svn: 116027
 2010-10-08 01:13:17 +00:00
Eric Christopher 3e1e447ca2 Remember to promote load/store types for stack to register size. 
llvm-svn: 115984
 2010-10-07 21:40:18 +00:00
Eric Christopher a2583ea9f2 Use the correct register class for load instructions - fixes 
compilation of MultiSource/Benchmarks/Bullet.

llvm-svn: 115907
 2010-10-07 05:50:44 +00:00
Eric Christopher 76a9752d45 Use the correct register class here. 
llvm-svn: 115906
 2010-10-07 05:39:19 +00:00