a6729e8666
Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's
...
return ValueType can depend its operands' ValueType.
This is a cosmetic change, no functionality impacted.
llvm-svn: 48145
2008-03-10 15:42:14 +00:00
d9d874b0cd
Codegen support for i128 SINT_TO_FP.
...
llvm-svn: 47928
2008-03-05 01:08:17 +00:00
0e238dc813
Yet more APInt-ification.
...
llvm-svn: 47867
2008-03-03 22:37:52 +00:00
2fa65b7997
More APInt-ification.
...
llvm-svn: 47866
2008-03-03 22:22:56 +00:00
cbde4c2206
Interface of getByValTypeAlignment differed between
...
generic & x86 versions; change generic to follow x86
and improve comments. Add PPC version (not right
for non-Darwin.)
llvm-svn: 47734
2008-02-28 22:31:51 +00:00
c799065cc3
Add a quick and dirty "loop aligner pass". x86 uses it to align its loops to 16-byte boundaries.
...
llvm-svn: 47703
2008-02-28 00:43:03 +00:00
ae2b6fbb8e
Convert SimplifyDemandedMask and ShrinkDemandedConstant to use APInt.
...
Change several cases in SimplifyDemandedMask that don't ever do any
simplifying to reuse the logic in ComputeMaskedBits instead of
duplicating it.
llvm-svn: 47648
2008-02-27 00:25:32 +00:00
c24ea4fb41
Change "Name" to "AsmName" in the target register info. Gee, a refactoring tool
...
would have been a Godsend here!
llvm-svn: 47625
2008-02-26 21:11:01 +00:00
ccc0c996a4
Refactor inline asm constraint matching code out of SDIsel into TargetLowering.
...
llvm-svn: 47587
2008-02-26 02:33:44 +00:00
1f372edd97
Convert MaskedValueIsZero and all its users to use APInt. Also add
...
a SignBitIsZero function to simplify a common use case.
llvm-svn: 47561
2008-02-25 21:11:39 +00:00
4c95dbd69f
In TargetLowering::LowerCallTo, don't assert that
...
the return value is zero-extended if it isn't
sign-extended. It may also be any-extended.
Also, if a floating point value was returned
in a larger floating point type, pass 1 as the
second operand to FP_ROUND, which tells it
that all the precision is in the original type.
I think this is right but I could be wrong.
Finally, when doing libcalls, set isZExt on
a parameter if it is "unsigned". Currently
isSExt is set when signed, and nothing is
set otherwise. This should be right for all
calls to standard library routines.
llvm-svn: 47122
2008-02-14 17:28:50 +00:00
53e1b3f9d5
Change how FP immediates are handled.
...
1) ConstantFP is now expand by default
2) ConstantFP is not turned into TargetConstantFP during Legalize
if it is legal.
This allows ConstantFP to be handled like Constant, allowing for
targets that can encode FP immediates as MachineOperands.
As a bonus, fix up Itanium FP constants, which now correctly match,
and match more constants! Hooray.
llvm-svn: 47121
2008-02-14 08:57:00 +00:00
e1d9ee66ed
Simplify some logic in ComputeMaskedBits. And change ComputeMaskedBits
...
to pass the mask APInt by value, not by reference.
llvm-svn: 47096
2008-02-13 22:28:48 +00:00
f990faf23b
Convert SelectionDAG::ComputeMaskedBits to use APInt instead of uint64_t.
...
Add an overload that supports the uint64_t interface for use by clients
that haven't been updated yet.
llvm-svn: 47039
2008-02-13 00:35:47 +00:00
3a4be0fdef
Rename MRegisterInfo to TargetRegisterInfo.
...
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
47a7d6fafe
Factor the addressing mode and the load/store VT out of LoadSDNode
...
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
llvm-svn: 46538
2008-01-30 00:15:11 +00:00
2b3bc30420
Handle 'X' constraint in asm's better.
...
llvm-svn: 46485
2008-01-29 02:21:21 +00:00
ec3da554e6
Forgot these.
...
llvm-svn: 46292
2008-01-24 00:22:01 +00:00
bc6cf9e810
remove extraneous &'s.
...
llvm-svn: 46171
2008-01-18 19:36:20 +00:00
1ea55cf816
This commit changes:
...
1. Legalize now always promotes truncstore of i1 to i8.
2. Remove patterns and gunk related to truncstore i1 from targets.
3. Rename the StoreXAction stuff to TruncStoreAction in TLI.
4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions.
5. Mark a wide variety of invalid truncstores as such in various targets, e.g.
X86 currently doesn't support truncstore of any of its integer types.
6. Add legalize support for truncstores with invalid value input types.
7. Add a dag combine transform to turn store(truncate) into truncstore when
safe.
The later allows us to compile CodeGen/X86/storetrunc-fp.ll to:
_foo:
fldt 20(%esp)
fldt 4(%esp)
faddp %st(1)
movl 36(%esp), %eax
fstps (%eax)
ret
instead of:
_foo:
subl $4, %esp
fldt 24(%esp)
fldt 8(%esp)
faddp %st(1)
fstps (%esp)
movl 40(%esp), %eax
movss (%esp), %xmm0
movss %xmm0, (%eax)
addl $4, %esp
ret
llvm-svn: 46140
2008-01-17 19:59:44 +00:00
ee8df1f4d3
Add support for targets that have a legal ISD::TRAP.
...
llvm-svn: 46014
2008-01-15 21:58:08 +00:00
53c954fa86
Output sinl for a long double FSIN node, not sin.
...
Likewise fix up a bunch of other libcalls. While
there I remove NEG_F32 and NEG_F64 since they are
not used anywhere. This fixes 9 Ada ACATS failures.
llvm-svn: 45833
2008-01-10 10:28:30 +00:00
96317d2412
fix typo duncan noticed!
...
llvm-svn: 45459
2007-12-30 21:21:10 +00:00
f3ebc3f3d2
Remove attribution from file headers, per discussion on llvmdev.
...
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
3b6a82118b
Fold comparisons against a constant nan, and optimize ORD/UNORD
...
comparisons with a constant. This allows us to compile isnan to:
_foo:
fcmpu cr7, f1, f1
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
instead of:
LCPI1_0: ; float
.space 4
_foo:
lis r2, ha16(LCPI1_0)
lfs f0, lo16(LCPI1_0)(r2)
fcmpu cr7, f1, f0
mfcr r2
rlwinm r3, r2, 0, 31, 31
blr
llvm-svn: 45405
2007-12-29 08:37:08 +00:00
de272b1b63
initial code for forming an FGETSIGN node. This is disabled until
...
legalizer support goes in.
llvm-svn: 45323
2007-12-22 21:35:38 +00:00
843cad4df2
Add a new FGETSIGN operation, which defaults to expand on all
...
targets.
llvm-svn: 45320
2007-12-22 20:47:56 +00:00
6f026a654c
Support returning non-power-of-2 vectors to unblock some work
...
llvm-svn: 44371
2007-11-27 19:28:48 +00:00
797d56ff17
Much improved pic jumptable codegen:
...
Then:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
imull $4, %ecx, %ecx
leal LJTI1_0-"L1$pb"(%eax), %edx
addl LJTI1_0-"L1$pb"(%ecx,%eax), %edx
jmpl *%edx
.align 2
.set L1_0_set_3,LBB1_3-LJTI1_0
.set L1_0_set_2,LBB1_2-LJTI1_0
.set L1_0_set_5,LBB1_5-LJTI1_0
.set L1_0_set_4,LBB1_4-LJTI1_0
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
Now:
call "L1$pb"
"L1$pb":
popl %eax
...
LBB1_1: # entry
addl LJTI1_0-"L1$pb"(%eax,%ecx,4), %eax
jmpl *%eax
.align 2
.set L1_0_set_3,LBB1_3-"L1$pb"
.set L1_0_set_2,LBB1_2-"L1$pb"
.set L1_0_set_5,LBB1_5-"L1$pb"
.set L1_0_set_4,LBB1_4-"L1$pb"
LJTI1_0:
.long L1_0_set_3
.long L1_0_set_2
llvm-svn: 43924
2007-11-09 01:32:10 +00:00
f14006f4d6
Didn't mean to check these in.
...
llvm-svn: 43923
2007-11-09 01:28:33 +00:00
1bf166312b
Bug fix. Passive nodes are not in SUnitMap.
...
llvm-svn: 43922
2007-11-09 01:27:11 +00:00
fa0df55bdd
Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
...
Thanks for the suggestions Bill :-)
llvm-svn: 43742
2007-11-05 23:12:20 +00:00
4646aa3e33
Make labels work in asm blocks; allow labels as
...
parameters. Rename ValueRefList to ParamList
in AsmParser, since its only use is for parameters.
llvm-svn: 43734
2007-11-05 21:20:28 +00:00
fd66486950
Add runtime library names for pow.
...
llvm-svn: 42880
2007-10-11 23:09:10 +00:00
a160361c85
Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} to
...
use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code
associated with these operators into target-independent in LegalizeDAG.cpp
and TargetLowering.cpp.
llvm-svn: 42762
2007-10-08 18:33:35 +00:00
c0154c06d6
First round of ppc long double. call/return and
...
basic arithmetic works.
Rename RTLIB long double functions to distinguish
different flavors of long double; the lib functions
have different names, alas.
llvm-svn: 42644
2007-10-05 20:04:43 +00:00
25a00a63eb
Add sqrt and powi intrinsics for long double.
...
llvm-svn: 42423
2007-09-28 01:08:20 +00:00
5e1a428344
Move the setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand) and
...
the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
llvm-svn: 42297
2007-09-25 15:10:49 +00:00
b3d01d2f56
initialize SetCCResultContents, fixing PR1693
...
llvm-svn: 42193
2007-09-21 17:06:39 +00:00
7d67e547b5
More long double fixes. x86_64 should build now.
...
llvm-svn: 42155
2007-09-19 23:55:34 +00:00
e2f23a3abf
Add lengthof and endof templates that hide a lot of sizeof computations.
...
Patch by Sterling Stein!
llvm-svn: 41758
2007-09-07 04:06:50 +00:00
d8c9cb9182
rename isOperandValidForConstraint to LowerAsmOperandForConstraint,
...
changing the interface to allow for future changes.
llvm-svn: 41384
2007-08-25 00:47:38 +00:00
ba1a98a4e0
long double 9 of N. This finishes up the X86-32 bits
...
(constants are still not handled). Adds ConvertActions
to control fp-to-fp conversions (these are currently
defaulted for all other targets, so no changes there).
llvm-svn: 40958
2007-08-09 01:04:01 +00:00
6decfbf133
Initialize the IndexedModeActions array with memset before
...
updating it with calls to setIndexedLoadAction/setIndexedStoreAction,
which only update a few bits at a time. This avoids ostensible
undefined behavior of operationg on values which may be
trap-representations, and as a practical matter fixes errors from
valgrind, which doesn't track uninitialized memory with bit
granularity.
llvm-svn: 38468
2007-07-09 20:49:44 +00:00
7867793aff
Add new TargetLowering code to provide the final register type that an
...
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.
Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.
llvm-svn: 37781
2007-06-28 23:29:44 +00:00
a866514528
Generalize MVT::ValueType and associated functions to be able to represent
...
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.
This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.
llvm-svn: 37719
2007-06-25 16:23:39 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
8e8d34b220
Tidy up ValueType names in comments.
...
llvm-svn: 37688
2007-06-21 14:48:26 +00:00
04deef3a49
Rename TargetLowering::getNumElements and friends to
...
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.
llvm-svn: 37687
2007-06-21 14:42:22 +00:00
397c4d9ef6
Fix CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll, and PR1473.
...
llvm-svn: 37362
2007-05-30 16:30:06 +00:00
1fa8276e70
same patch as the previous one, but the symmetric case
...
llvm-svn: 37249
2007-05-19 00:46:51 +00:00
b08cbbd737
Disable the (A == (B-A)) -> 2*A == B xform when the sub has multiple uses (in
...
this case, the xform introduces an extra operation). This compiles
PowerPC/compare-duplicate.ll into:
_test:
subf r2, r3, r4
cmplw cr0, r2, r3
bne cr0, LBB1_2 ;F
instead of:
_test:
slwi r2, r3, 1
subf r3, r3, r4
cmplw cr0, r4, r2
bne cr0, LBB1_2 ;F
This is target independent of course.
llvm-svn: 37246
2007-05-19 00:43:44 +00:00
1796f1f8e9
Qualify several calls to functions in the MVT namespace, for consistency.
...
llvm-svn: 37230
2007-05-18 17:52:13 +00:00
0184f88deb
disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for
...
i128 integers. The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.
llvm-svn: 37169
2007-05-17 18:19:23 +00:00
429178d727
Add target hook to specify block size limit for if-conversion.
...
llvm-svn: 37134
2007-05-16 23:45:53 +00:00
44a2ed66b1
Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll
...
and PR1382
llvm-svn: 36672
2007-05-03 16:54:34 +00:00
15c1b820cc
fix a pasto
...
llvm-svn: 36242
2007-04-18 03:01:40 +00:00
4aff52bf3d
Fix a bug in my previous patch, grabbing the shift amount width from the
...
wrong operand.
llvm-svn: 36223
2007-04-17 22:53:02 +00:00
9a861a8550
Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used.
...
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
srwi r2, r3, 1
extsh r3, r2
blr
on PPC, instead of:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
GCC produces:
_baz:
srwi r10,r4,24
insrwi r10,r3,24,0
srawi r9,r3,24
srawi r3,r10,9
extsh r3,r3
blr
This implements CodeGen/PowerPC/shl_elim.ll
llvm-svn: 36221
2007-04-17 21:14:16 +00:00
fb80151c42
Removed tabs everywhere except autogenerated & external files. Add make
...
target for tabs checking.
llvm-svn: 36146
2007-04-16 18:10:23 +00:00
784a68a702
Fix weirdness handling single element vectors.
...
llvm-svn: 35941
2007-04-12 04:44:28 +00:00
35f0417ec1
remove dead target hooks.
...
llvm-svn: 35847
2007-04-09 23:34:08 +00:00
39f65335d5
remove some dead target hooks, subsumed by isLegalAddressingMode
...
llvm-svn: 35840
2007-04-09 22:27:04 +00:00
f2d71d49e2
switch TL::getValueType to use MVT::getValueType.
...
llvm-svn: 35527
2007-03-31 04:05:24 +00:00
ac3f81508c
add one addressing mode description hook to rule them all.
...
llvm-svn: 35520
2007-03-30 23:14:50 +00:00
c2cba18f2b
Remove isLegalAddressImmediate.
...
llvm-svn: 35406
2007-03-28 01:53:55 +00:00
3d7efa2586
implement initial support for the silly X constraint. Testcase here: CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
...
llvm-svn: 35327
2007-03-25 04:35:41 +00:00
843e44503c
Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll
...
llvm-svn: 35324
2007-03-25 02:18:14 +00:00
d685514e2e
switch TargetLowering::getConstraintType to take the entire constraint,
...
not just the first letter. No functionality change.
llvm-svn: 35322
2007-03-25 02:14:49 +00:00
0c6bb5eab7
repair x86 performance, dejagnu problems from previous change
...
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
bacf4acf65
do not share old induction variables when this would result in invalid
...
instructions (that would have to be split later)
llvm-svn: 35227
2007-03-20 21:54:54 +00:00
a2a2fd1e55
Added isLegalAddressExpression hook to test if the given expression can be
...
folded into target addressing mode for the given type.
llvm-svn: 35121
2007-03-16 08:42:32 +00:00
b7004fd889
More flexible TargetLowering LSR hooks for testing whether an immediate is a legal target address immediate or scale.
...
llvm-svn: 35076
2007-03-12 23:37:10 +00:00
168c5856bf
initialize a instance variable
...
llvm-svn: 34567
2007-02-25 01:28:05 +00:00
d7ef3f804d
Fix CodeGen/Generic/2007-02-23-DAGCombine-Miscompile.ll and PR1219
...
llvm-svn: 34551
2007-02-24 02:09:29 +00:00
3e3a65b764
Need to init.
...
llvm-svn: 34499
2007-02-22 18:04:49 +00:00
a9f917af59
Implement i/n/s constraints correctly. This fixes
...
test/CodeGen/PowerPC/2007-02-16-InlineAsmNConstraint.ll
llvm-svn: 34368
2007-02-17 06:00:35 +00:00
d84d35ba70
For PR1195:
...
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.
llvm-svn: 34293
2007-02-15 02:26:10 +00:00
d08d31f68a
Fix PR1198, by adding initial i128 support. Patch by Dan Gohman.
...
llvm-svn: 34256
2007-02-13 23:41:38 +00:00
92658d5648
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
...
llvm-svn: 34065
2007-02-08 22:13:59 +00:00
296a83cefb
Fit in 80 columns
...
llvm-svn: 33745
2007-02-01 04:55:59 +00:00
53026f1d5a
Allow the target to override the ISD::CondCode that's to be used to test the
...
result of the comparison libcall against zero.
llvm-svn: 33701
2007-01-31 09:29:11 +00:00
ddf1421b8e
Move a function out of line.
...
llvm-svn: 33158
2007-01-12 23:30:31 +00:00
61a4be88b4
Minor fix.
...
llvm-svn: 33149
2007-01-12 22:51:10 +00:00
31cbddf28a
Store default libgcc routine names and allow them to be redefined by target.
...
llvm-svn: 33105
2007-01-12 02:11:51 +00:00
3b7c257cae
Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
...
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.
llvm-svn: 32415
2006-12-10 23:12:42 +00:00
4eee72471c
Preliminary soft float support.
...
llvm-svn: 32394
2006-12-09 02:42:38 +00:00
5d5916b4d1
Fix the dag combiner bug corresponding to PR1014.
...
llvm-svn: 31943
2006-11-27 21:50:02 +00:00
d550248f2c
Add a mechanism to specify whether a target supports a particular indexed load / store.
...
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
de46e48420
For PR786:
...
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
llvm-svn: 31380
2006-11-02 20:25:50 +00:00
8c6949e5b2
Change the prototype for TargetLowering::isOperandValidForConstraint
...
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
d35734bd1f
Naming consistency.
...
llvm-svn: 30878
2006-10-11 07:10:22 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
a389a612bb
initialize ivar
...
llvm-svn: 30780
2006-10-06 22:52:08 +00:00
5d9fd977d3
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
...
extra operand to LOADX to specify the exact value extension type.
llvm-svn: 30714
2006-10-04 00:56:09 +00:00
0dce3311c4
Change the default to 0, which means 'default'.
...
llvm-svn: 30114
2006-09-05 17:39:15 +00:00
373be1d1a2
forgot this
...
llvm-svn: 30097
2006-09-04 07:44:11 +00:00
85ea83e821
Add some advice
...
llvm-svn: 29324
2006-07-27 04:24:14 +00:00
Scott Michel