f1b225d0e0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
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the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
llvm-svn: 157019
2012-05-17 22:18:01 +00:00
5a719f9b9a
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
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llvm-svn: 156608
2012-05-11 09:10:54 +00:00
f435b09eaf
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
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llvm-svn: 155700
2012-04-27 08:42:59 +00:00
c407cc7a40
For ARM disassembly only print 32 unsigned bits for the address of branch
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targets so if the branch target has the high bit set it does not get printed as:
beq 0xffffffff8008c404
llvm-svn: 154685
2012-04-13 18:46:37 +00:00
1c0541b031
Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.
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All implementations used the same code.
llvm-svn: 153866
2012-04-02 08:32:38 +00:00
dab9e35ad0
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.
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llvm-svn: 153863
2012-04-02 07:01:04 +00:00
54bfde79db
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.
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llvm-svn: 153860
2012-04-02 06:09:36 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
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Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
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Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
63ee881cd6
Tidy up. Kill some dead code.
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llvm-svn: 152131
2012-03-06 18:59:19 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
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Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
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With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
fd93a59557
Make MCRegisterInfo available to the the MCInstPrinter.
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Used to allow context sensitive printing of super-register or sub-register
references.
llvm-svn: 152043
2012-03-05 19:33:20 +00:00
f0269b4270
Change ARMInstPrinter::printPredicateOperand() so it will not abort if it
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runs into the undefined 15 condition code value.
llvm-svn: 151844
2012-03-01 22:13:02 +00:00
636a3d618c
Remove dead code. Improve llvm_unreachable text. Simplify some control flow.
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llvm-svn: 150918
2012-02-19 11:37:01 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
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llvm-svn: 149961
2012-02-07 02:50:20 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
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llvm-svn: 148884
2012-01-25 00:01:08 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
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llvm-svn: 148882
2012-01-24 23:47:04 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
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llvm-svn: 148762
2012-01-24 00:43:17 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
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llvm-svn: 148745
2012-01-23 23:20:46 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
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rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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llvm-svn: 147025
2011-12-21 00:38:54 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
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rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
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Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
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llvm-svn: 146409
2011-12-12 19:48:00 +00:00
3ecf976ca9
ARM parsing for VLD1 two register all lanes, no writeback.
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llvm-svn: 145504
2011-11-30 18:21:25 +00:00
cd6f5e757c
ARM parsing aliases for VLD1 single register all lanes.
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llvm-svn: 145464
2011-11-30 01:09:44 +00:00
539d0a8a09
build/CMake: Finish removal of add_llvm_library_dependencies.
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llvm-svn: 145420
2011-11-29 19:25:30 +00:00
69d57cf9c4
Simplify some uses of utohexstr.
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As a side effect hex is printed lowercase instead of uppercase now.
llvm-svn: 144013
2011-11-07 21:00:59 +00:00
bf9bba47a1
build: Add initial cut at LLVMBuild.txt files.
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llvm-svn: 143634
2011-11-03 18:53:17 +00:00
fbb704f551
Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction.
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llvm-svn: 143557
2011-11-02 18:03:14 +00:00
846bcff7c7
Assembly parsing for 4-register variant of VLD1.
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llvm-svn: 142682
2011-10-21 20:35:01 +00:00
c4360fe575
Assembly parsing for 3-register variant of VLD1.
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llvm-svn: 142675
2011-10-21 20:02:19 +00:00
2f2e3c4737
ARM VLD parsing and encoding.
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Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
llvm-svn: 142670
2011-10-21 18:54:25 +00:00
20cb505e2f
whitespace.
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llvm-svn: 142657
2011-10-21 16:56:40 +00:00
ad47cfcef9
ARM VTBL (one register) assembly parsing and encoding.
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llvm-svn: 142441
2011-10-18 23:02:30 +00:00
483995875f
ARM parsing and encoding for the <option> form of LDC/STC instructions.
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llvm-svn: 141786
2011-10-12 17:34:41 +00:00
d74c0e7c14
80 columns.
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llvm-svn: 141781
2011-10-12 16:36:01 +00:00
6966411f45
Tidy up. Formatting.
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llvm-svn: 141780
2011-10-12 16:34:37 +00:00
d0637bfc68
ARM NEON assembly parsing and encoding for VDUP(scalar).
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llvm-svn: 141446
2011-10-07 23:56:00 +00:00
10c5b12f99
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
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llvm-svn: 141190
2011-10-05 17:16:40 +00:00
5dcda64338
Adding back support for printing operands symbolically to ARM's new disassembler
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using llvm's public 'C' disassembler API now including annotations.
Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
blx _puts
instead of this:
blx #-36
and includes support for annotations for branches to symbol stubs like:
bl 0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
ldr r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
movt r0, :upper16:((_foo-_bar)+1234)
llvm-svn: 141129
2011-10-04 22:44:48 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
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Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
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Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
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llvm-svn: 140420
2011-09-23 21:26:40 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
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llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
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llvm-svn: 140283
2011-09-21 23:44:46 +00:00
bcc3fadad9
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
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llvm-svn: 140267
2011-09-21 17:58:45 +00:00
69fa8ffeef
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
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llvm-svn: 140217
2011-09-21 00:25:23 +00:00
Kevin Enderby