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157 Commits

Author SHA1 Message Date
Zoran Jovanovic 2960f3a346 [mips][microMIPS] Implement CACHEE, WRPGPR and WSBH instructions 
Differential Revision: http://reviews.llvm.org/D10337

llvm-svn: 249004
 2015-10-01 12:49:27 +00:00
Daniel Sanders df19a5e605 [mips][microMIPS] Fix an invalid read for lwm32 and reserved reglist values. 
Summary:
Some values of 'reglist' are reserved and cause the disassembler to read past
the end of the Regs array. Treat lwm32's containing reserved values as invalid
instructions.

Reviewers: zoran.jovanovic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D12959

llvm-svn: 247990
 2015-09-18 14:20:54 +00:00
Zoran Jovanovic 7ba636cb4c [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructions 
Differential Revision: http://reviews.llvm.org/D9658

llvm-svn: 247880
 2015-09-17 10:14:09 +00:00
Zoran Jovanovic 6e6a2c9cd7 [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and SWE instructions 
Differential Revision: http://reviews.llvm.org/D9189

llvm-svn: 247780
 2015-09-16 09:14:35 +00:00
Zoran Jovanovic dc4b8c2761 [mips][microMIPS] Fix an issue with disassembling lwm32 instruction 
Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer.
Differential Revision: http://reviews.llvm.org/D12881

llvm-svn: 247698
 2015-09-15 15:21:27 +00:00
Zoran Jovanovic 7beb737b46 [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6 
Differential Revision: http://reviews.llvm.org/D11632

llvm-svn: 247670
 2015-09-15 10:05:10 +00:00
Daniel Sanders e4e83a7bc1 [mips] Added support for various EVA ASE instructions. 
Summary:
Added support for the following instructions:

CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE,
SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF

This required adding some infrastructure for the EVA ASE.

Patch by Scott Egerton.

Reviewers: vkalintiris, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11139

llvm-svn: 247669
 2015-09-15 10:02:16 +00:00
Daniel Sanders 715f8f1332 [mips] Add missing disassembler tests for MIPS64-MIPS64R5. 
llvm-svn: 247422
 2015-09-11 16:24:11 +00:00
Daniel Sanders 9676db005e [mips] Add missing MIPS32 - MIPS32R5 disassembler tests. 
llvm-svn: 247420
 2015-09-11 15:28:19 +00:00
Daniel Sanders aba4daab10 [mips] Attempt to fix llvm-s390x-linux1 
It doesn't seem to like the '|&' in the test command.

llvm-svn: 247418
 2015-09-11 14:57:54 +00:00
Daniel Sanders 9bbda77006 [mips] Add missing MIPS-IV disassembler tests. 
llvm-svn: 247417
 2015-09-11 14:54:58 +00:00
Daniel Sanders ff338fa355 [mips] Add missing MIPS-III disassembler tests. 
llvm-svn: 247416
 2015-09-11 14:48:46 +00:00
Daniel Sanders 3b571d05f8 [mips] Add missing MIPS-II disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and were verified by checking the disassembler output is accepted by GAS.

llvm-svn: 247414
 2015-09-11 14:34:41 +00:00
Daniel Sanders 44c1d0c4f1 Re-commit r247405: [mips] Add missing MIPS-I disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and verified by checking the disassembler output is accepted by GAS.

The problematic tests from the previous commit have been moved to
valid-xfail.txt for now.

Also, give invalid instructions some coverage. invalid-xfail.txt contains
instructions that should be invalid but successfully disassemble.

llvm-svn: 247407
 2015-09-11 12:59:03 +00:00
Daniel Sanders c6a2034d0f Revert r247405: [mips] Add missing MIPS-I disassembler tests. 
A small number of the added tests have operands that change on each round trip.

llvm-svn: 247406
 2015-09-11 12:42:38 +00:00
Daniel Sanders f05bf32b38 [mips] Add missing MIPS-I disassembler tests. 
These tests were found by llvm-mc-fuzzer (see http://reviews.llvm.org/D12723)
and verified by checking the disassembler output is accepted by GAS.

llvm-svn: 247405
 2015-09-11 12:24:06 +00:00
Zoran Jovanovic 6b28f09d67 [mips][microMIPS] Implement ADDU16, AND16, ANDI16, NOT16, OR16, SLL16 and SRL16 instructions 
Differential Revision: http://reviews.llvm.org/D11178

llvm-svn: 247146
 2015-09-09 13:55:45 +00:00
Zoran Jovanovic d9790793d6 [mips][microMIPS] Implement CACHEE and PREFE instructions 
Differential Revision: http://reviews.llvm.org/D11628

llvm-svn: 247125
 2015-09-09 09:10:46 +00:00
Zoran Jovanovic 2da1437d62 [mips][microMIPS] Implement LLE, LUI, LW and LWE instructions 
Differential Revision: http://reviews.llvm.org/D1179

llvm-svn: 247017
 2015-09-08 15:02:50 +00:00
Zoran Jovanovic 9eaa30d2bf [mips][microMIPS] Implement SB, SBE, SCE, SH and SHE instructions 
Differential Revision: http://reviews.llvm.org/D11801

llvm-svn: 246999
 2015-09-08 10:18:38 +00:00
Zoran Jovanovic 68be5f21a9 [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit LBU16, LHU16, LW16, LWGP and LWSP instructions 
Differential Revision: http://reviews.llvm.org/D10956

llvm-svn: 246987
 2015-09-08 08:25:34 +00:00
Zoran Jovanovic 7b85682541 [mips][microMIPS] Implement ABS.fmt, CEIL.L.fmt, CEIL.W.fmt, FLOOR.L.fmt, FLOOR.W.fmt, TRUNC.L.fmt, TRUNC.W.fmt, RSQRT.fmt and SQRT.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11674

llvm-svn: 246968
 2015-09-07 13:01:04 +00:00
Zoran Jovanovic ada7091812 [mips][microMIPS] Implement BC16, BEQZC16 and BNEZC16 instructions 
Differential Revision: http://reviews.llvm.org/D11181

llvm-svn: 246963
 2015-09-07 11:56:37 +00:00
Zoran Jovanovic 14f308e44f [mips][microMIPS] Implement CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, MAX.fmt, MIN.fmt, MAXA.fmt, MINA.fmt and CMP.condn.fmt instructions 
Differential Revision: http://reviews.llvm.org/D12141

llvm-svn: 246960
 2015-09-07 10:31:31 +00:00
Zoran Jovanovic 89ca2b982e [mips][microMIPS] Implement ADD.fmt, SUB.fmt, MOV.fmt, MUL.fmt, DIV.fmt, MADDF.fmt, MSUBF.fmt and NEG.fmt instructions 
Differential Revision: http://reviews.llvm.org/D11978

llvm-svn: 246919
 2015-09-05 09:25:30 +00:00
Zoran Jovanovic 56585d517b [mips][microMIPS] Add microMIPS32r6 and microMIPS64r6 tests for existing 16-bit ADDIUR1SP, ADDIUR2, ADDIUS5 and ADDIUSP instructions 
Differential Revision: http://reviews.llvm.org/D10955

llvm-svn: 245554
 2015-08-20 11:51:49 +00:00
Zoran Jovanovic 2fe8466f6e [mips][microMIPS] Implement DDIV, DMOD, DDIVU and DMODU instructions 
Differential Revision: http://reviews.llvm.org/D10953

llvm-svn: 245297
 2015-08-18 14:40:43 +00:00
Zoran Jovanovic a6593ff613 [mips][microMIPS] Implement SW and SWE instructions 
Differential Revision: http://reviews.llvm.org/D10869

llvm-svn: 245293
 2015-08-18 12:53:08 +00:00
Zoran Jovanovic 366783e14c [mips][microMIPS] Create microMIPS64r6 subtarget and implement DALIGN, DAUI, DAHI, DATI, DEXT, DEXTM and DEXTU instructions 
Differential Revision: http://reviews.llvm.org/D10923

llvm-svn: 244744
 2015-08-12 12:45:16 +00:00
Vasileios Kalintiris 1c78ca6a09 [mips] Remap move as or. 
Summary:
This patch remaps the assembly idiom 'move' to 'or' instead of 'daddu' or
'addu'. The use of addu/daddu instead of or as move was highlighted as a
performance issue during the analysis of a recent 64bit design. Originally
move was encoded as 'or' by binutils but was changed for the r10k cpu family
due to their pipeline which had 2 arithmetic units and a single logical unit,
and so could issue multiple (d)addu based moves at the same time but only 1
logical move.

This patch preserves the disassembly behaviour so that disassembling a old style
(d)addu move still appears as move, but assembling move always gives an or

Patch by Simon Dardis.

Reviewers: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11796

llvm-svn: 244579
 2015-08-11 08:56:25 +00:00
Vasileios Kalintiris 974d409259 [mips] Added support for the ERETNC instruction. 
Summary: This required adding the instruction predicate HasMips32r5.

Patch by Scott Egerton.

Reviewers: dsanders, vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11136

llvm-svn: 242666
 2015-07-20 12:28:56 +00:00
Zoran Jovanovic 2a47d08afd [mips][microMIPS] Implement SLL and NOP instructions 
http://reviews.llvm.org/D10474

llvm-svn: 241150
 2015-07-01 09:54:51 +00:00
Daniel Sanders b2fa8add82 [mips] Fold duplicate big-endian disassembler tests together. 
llvm-svn: 240887
 2015-06-27 17:56:44 +00:00
Daniel Sanders abe7d840b9 [mips] Sort big-endian disassembler tests by opcode. 
llvm-svn: 240885
 2015-06-27 16:13:59 +00:00
Daniel Sanders de692cae9d [mips] Make little-endian disassembler test filenames consistent. 
Most are named *-el.txt. Renamed the three that were *-le.txt

llvm-svn: 240884
 2015-06-27 15:42:25 +00:00
Daniel Sanders a3134fae17 [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0. 
Summary:
Previously it (incorrectly) used GPR's.

Patch by Simon Dardis. A couple small corrections by myself.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10567

llvm-svn: 240883
 2015-06-27 15:39:19 +00:00
Zoran Jovanovic 67e04be640 [mips][microMIPS] Implement BREAK, EHB and EI instructions 
http://reviews.llvm.org/D10090

llvm-svn: 240531
 2015-06-24 10:32:16 +00:00
Zoran Jovanovic cdfcbe41f2 [mips][microMIPS] Implement ERET and ERETNC instructions 
http://reviews.llvm.org/D10091

llvm-svn: 239522
 2015-06-11 10:22:46 +00:00
Zoran Jovanovic fcecf26092 [mips][microMIPSr6] Change disassembler tests to one line format 
llvm-svn: 239519
 2015-06-11 09:42:10 +00:00
Zoran Jovanovic 85a53a1ed5 [mips][microMIPSr6] Implement SEB and SEH instructions 
Differential Revision: http://reviews.llvm.org/D9739

llvm-svn: 238333
 2015-05-27 15:39:47 +00:00
Jozef Kolek 888830adfe [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions 
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031

llvm-svn: 238325
 2015-05-27 14:19:22 +00:00
Zoran Jovanovic dde61c00c3 [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions 
Differential Revision: http://reviews.llvm.org/D8800

llvm-svn: 237697
 2015-05-19 14:12:55 +00:00
Zoran Jovanovic 299fed6b7d [mips][microMIPSr6] Implement AND and ANDI instructions 
Differential Revision: http://reviews.llvm.org/D8772

llvm-svn: 237696
 2015-05-19 13:32:31 +00:00
Zoran Jovanovic 3825261572 [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions 
Differential Revision: http://reviews.llvm.org/D8769

llvm-svn: 237685
 2015-05-19 11:21:37 +00:00
Jozef Kolek cc0c0fc926 [mips][microMIPSr6] Implement LSA instruction 
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919

llvm-svn: 237634
 2015-05-18 23:12:10 +00:00
Jozef Kolek cbb227b48d [mips][microMIPSr6] Implement ALIGN and AUI instructions 
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782

llvm-svn: 237563
 2015-05-18 11:44:30 +00:00
Jozef Kolek 6fec325d10 [mips][microMIPSr6] Implement CLO and CLZ instructions 
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553

llvm-svn: 237257
 2015-05-13 14:18:11 +00:00
Jozef Kolek 38bb81db85 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions 
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497

llvm-svn: 237158
 2015-05-12 17:39:32 +00:00
Jozef Kolek 8abad7bacc [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions 
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441

llvm-svn: 236858
 2015-05-08 14:25:11 +00:00
Jozef Kolek 9ce6e0a926 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions 
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415

llvm-svn: 236852
 2015-05-08 13:52:04 +00:00